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參數(shù)資料
| 型號： | XR16C2850IP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| 中文描述： | 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 12/43頁 |
| 文件大小： | 611K |
| 代理商： | XR16C2850IP |
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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
12
2.11 R
ECEIVER
The receiver section contains an 8-bit Receive Shift
Register (RSR) and 128 bytes of FIFO which includes
a byte-wide Receive Holding Register (RHR). The
RSR uses the 16X/8X clock (CLK8/16 pin) for timing.
It verifies and validates every bit on the incoming
character in the middle of each data bit. On the falling
edge of a start or false start bit, an internal receiver
counter starts counting at the 16X/8X clock rate. After
8 clocks (or 4 if 8X) the start bit period should be at
the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evalu-
ating the start bit in this manner prevents the receiver
from assembling a false character. The rest of the da-
ta bits and stop bits are sampled and validated in this
same manner to prevent false framing. If there were
any error(s), they are reported in the LSR register bits
2-4. Upon unloading the receive data byte from RHR,
the receive FIFO pointer is bumped and the error tags
are immediately updated to reflect the status of the
data byte in RHR register. RHR can generate a re-
ceive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Fur-
thermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not
received for 4 word lengths as defined by LCR[1:0]
plus 12 bits time. This is equivalent to 3.7-4.6 charac-
ter times. The RHR interrupt is enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-
Only
The Receive Holding Register is an 8-bit register that
holds a receive data byte from the Receive Shift Reg-
ister. It provides the receive data interface to the host
processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are
for the 3 error tags to be reported in LSR register.
When the FIFO is enabled by FCR bit-0, the RHR
contains the first data character received by the FIFO.
After the RHR is read, the next character byte is load-
ed into the RHR and the errors associated with the
current data byte are immediately updated in the LSR
bits 2-4.
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X
Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
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| XR16C2852 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852CJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852IJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C850CJ | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IP40 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2852 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
| XR16C2852CJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C2852CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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