參數(shù)資料
型號(hào)： XR16C2850IP40
廠商： EXAR CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 41/43頁(yè)
文件大?。?/td> 611K
代理商： XR16C2850IP40
áy
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
41
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2002 EXAR Corporation
Datasheet April 2002
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
Date
Revision
Description
February 2000
Rev 1.0.0
Initial datasheet.
April 2002
Rev 2.0.0
Changed to standard style format. Internal Registers are described in the order
they are listed in the Internal Register Table. Clarified timing diagrams. Cor-
rected Auto RTS Hysteresis table. Renamed Rclk (Receive Clock) to Bclk (Baud
Clock) and timing symbols. Added T
AH
, T
CS
and OSC.
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