REV. 2.1.3 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 33 EMSR[5:4]: Extended RTS Hysteresis EMSR[7:6]: Reserved 4.12 FI" />
參數(shù)資料
型號: XR16C2850IJTR-F
廠商: Exar Corporation
文件頁數(shù): 27/51頁
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標準包裝: 500
特點: *
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
xr
XR16C2850
REV. 2.1.3
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
33
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
4.12
FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12 for details.
4.13
Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x12 for XR16C2850). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
TABLE 13: EXTENDED RTS HYSTERESIS
EMSR
BIT-5
EMSR
BIT-4
FCTR
BIT-1
FCTR
BIT-0
RTS#
HYSTERESIS
(CHARACTERS)
0
1
±4
0
1
0
±6
0
1
±8
0
1
0
±8
0
1
0
1
±16
0
1
0
±24
0
1
±32
1
0
±40
1
0
1
±44
1
0
1
0
±48
1
0
1
±52
1
0
±12
1
0
1
±20
1
0
±28
1
±36
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