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參數(shù)資料
| 型號： | XR16C2850CP40 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 7/43頁 |
| 文件大?。?/td> | 611K |
| 代理商： | XR16C2850CP40 |
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XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
7
2.0
2.1
The CPU interface is 8 data bits wide with 3 address
lines and control signals to execute data bus read and
write transactions. The 2850 data interface supports
the Intel compatible types of CPUs and it is compati-
ble to the industry standard 16C550 UART. No clock
FUNCTIONAL DESCRIPTIONS
CPU I
NTERFACE
(oscillator nor external clock) is required to operate a
data bus transaction. Each bus cycle is asynchronous
using CS#, IOR# and IOW# signals. Both UART
channels share the same data bus for host opera-
tions. The data bus interconnections are shown in
Figure 3.
2.2
The RESET input resets the internal registers and the
serial interface outputs in both channels to their de-
fault state (see Table 16 on page 30). An active high
pulse of longer than 40 ns duration will be required to
activate the reset function in the device.
2.3
D
EVICE
I
DENTIFICATION
AND
R
EVISION
The XR16C2850 provides a Device Identification
code and a Device Revision code to distinguish the
part from other devices and revisions. To read the
identification code from the part, it is required to set
the baud rate generator registers DLL and DLM both
to 0x00. Now reading the content of the DLM will pro-
vide 0x12 for the XR16C2850 and reading the con-
tent of DLL will provide the revision of the part; for ex-
ample, a reading of 0x01 means revision A.
2.4
C
HANNEL
A
AND
B S
ELECTION
The UART provides the user with the capability to bi-
directionally transfer information between an external
D
EVICE
R
ESET
CPU and an external serial communication device. A
logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure,
send transmit data and/or unload receive data to/from
the UART. Selecting both UARTs can be useful dur-
ing power up initialization to write to the same internal
registers, but do not attempt to read from both uarts
simultaneously. Individual channel select functions
are shown in Table 1.
F
IGURE
3. XR16C2850 D
ATA
B
US
I
NTERCONNECTIONS
VCC
VCC
OP2A#
DSRA#
CDA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RA#
OP2B#
DSRB#
CDB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channe A
UART
Channe B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYB#
TXRDYA#
RXRDYA#
TXRDYB#
TXRDYA#
RXRDYB#
RXRDYB#
UART_RESET
RESET
Seria Interface of
RS-232, RS-485
Seria Interface of RS-
232, RS-485
2750nt
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
CSA#
CSB#
F
UNCTION
1
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
0
Channel A and B selected
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16C2850IJ44 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IM48 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IP40 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850CJ | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
| XR16C2850CM | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C2850IJ | 制造商:Exar Corporation 功能描述:UART 2-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC 制造商:Rochester Electronics LLC 功能描述: |
| XR16C2850IJ44 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C2850IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2850IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS |
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