參數(shù)資料
型號(hào): XR16C2850CM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, EIAJ, TQFP-48
文件頁(yè)數(shù): 37/43頁(yè)
文件大小: 611K
代理商: XR16C2850CM
XR16C2850
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
37
F
IGURE
22. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A & B
TX
TXRDY#
IOW#
(Loading data
into FIFO)
INT*
TXDMA#
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
(Unloading)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
Data in
TX FIFO
TX FIFO
Empty
T
WT
T
SRT
TX FIFO
Empty
T
T
S
T
SI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
F
IGURE
23. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A & B
TX
TXRDY#
IOW#
(Loading data
into FIFO)
INT*
D0:D7
S
TXDMA
D0:D7
S
D0:D7
T
D0:D7
S
D0:D7
S
T
D0:D7
S
T
T
D0:D7
S
T
Start
Bit
Stop
Bit
T
WRI
T
(Unloading)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
T
SRT
TX FIFO
Full
T
WT
T
SI
ISR Read
ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
相關(guān)PDF資料
PDF描述
XR16C2850CP DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IJ DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IM DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IP DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2852 3.3V AND 5V DUART WITH 128-BYTE FIFO
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