參數(shù)資料
型號: XR16C2850CJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
中文描述: 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 30/43頁
文件大小: 611K
代理商: XR16C2850CJ
á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
30
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled
(default).
Logic 1 = Enable Automatic CTS flow control. Data
transmission stops when CTS# input de-asserts to
logic 1. Data transmission resumes when CTS#
returns to a logic 0.
4.20 S
OFTWARE
F
LOW
C
ONTROL
R
EGISTERS
(XOFF1,
XOFF2, XON1, XON2) - R
EAD
/W
RITE
These registers are used as the programmable soft-
ware flow control characters xoff1, xoff2, xon1, and
xon2. For more details, see Table 6 on page 15.
T
ABLE
16: UART RESET CONDITIONS FOR
CHANNEL A AND B
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
FCR
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs
inverted
SPR
Bits 7-0 = 0xFF
EMSR
Bits 7-0 = 0x00
FLVL
Bits 7-0 = 0x00
EFR
Bits 7-0 = 0x00
XON1
Bits 7-0 = 0x00
XON2
Bits 7-0 = 0x00
XOFF1
Bits 7-0 = 0x00
XOFF2
Bits 7-0 = 0x00
FC
Bits 7-0 = 0x00
I/O SIGNALS
RESET STATE
TX
Logic 1
OP2#
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RXRDY#
Logic 1
TXRDY#
Logic 0
INT
Three-State Condition
相關(guān)PDF資料
PDF描述
XR16C2850CM DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850CP DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
XR16C2850IJ DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL
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