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參數(shù)資料
| 型號： | XR-T7296 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3/STS-1, E3 Integrated Line Transmitter |
| 中文描述： | DS3/STS-1，E3類綜合線變送器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 187K |
| 代理商： | XR-T7296 |
XR-T7296
3
Rev. 2.01
PIN CONFIGURATION
RNDATA
RPDATA
ICT
TXLEV
V
DD
A
TTIP
TRING
GNDA
MTIP
MRING
DMO
RCLKO
RPOS
RNEG
RCLK
RLOOP
LLOOP
DS3,STS-1/E3
TAOS
V
DD
D
TPDATA
TNDATA
TCLK
GNDD
ENCODIS
DECODIS
BPV
RNRZ
28 Lead SOJ (Jedec, 0.300”)
28
1
15
14
2
3
4
5
6
7
17
16
8
9
19
18
10
11
23
22
21
20
27
26
25
24
12
13
RNDATA
RPDATA
ICT
TXLEV
V
DD
A
TTIP
TRING
GNDA
MTIP
MRING
DMO
RCLKO
RPOS
RNEG
RCLK
RLOOP
LLOOP
DS3,STS-1/E3
TAOS
V
DD
D
TPDATA
TNDATA
TCLK
GNDD
ENCODIS
DECODIS
BPV
RNRZ
28 Lead PDIP (0.600”)
13
16
14
15
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11
18
12
17
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
CLK
I
Receive Clock Input.
Input sampling clock for RPDATA and RNDATA.
2
RLOOP
I
Remote Loop Back.
A high on this pin causes RPDATA and RNDATA to transmitted to the
line using RCLK. Setting RLOOP and LLOOP high simultaneously is not permitted.
Local Loop Back.
A high on this pin causes TPDATA and TNDATA to pass through the en-
coder and output at RPOS and RNEG respectively. Setting LLOOP and RLOOP high simulta-
neously is not permitted.
3
LLOOP
I
4
DS3,STS-1/
E3
I
DS3, STS-1 or E3 Select Pin
. A high on this pin selects DS3 or STS-1 operation and sets the
encoder and decoder in B3ZS mode. A low selects E3 and sets the encoder and decoder in
HDB3 mode.
5
TAOS
I
Transmit All Ones Select
. A high on this pin causes a continuous AMI all 1’s pattern to be
transmitted to the line. The frequency is determined by TCLK.
5 V Digital Supply
(
5%) for all logic circuitry.
6
V
DD
D
TPDATA
7
I
Transmit Positive Data
. TPDATA is sampled on the falling edge of TCLK. Pin 7 and pin 8
can be tied together for binary input signals.
Transmit Negative Data.
TNDATA is sampled on the falling edge of TCLK. Pin 7 and pin 8
can be tied together for binary input signals.
Transmit Clock
for TPDATA and TNDATA.
8
TNDATA
I
9
TCLK
I
10
GNDD
Digital Ground
for all logic circuitry.
11
ENCODIS
I
Encoder Disable.
A high on this pin disables B3ZS or HDB3 encoding functions, unless over-
ridden by TAOS request. This pin must be set high if TPDATA and TNDATA are already en-
coded.
12
DECODIS
I
Decoder Disable
. A high on this pin disables B3ZS or HDB3 decoding functions.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7296_10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:XRT7296 DS3 STS-1 E3 Integrated Line Transmitter |
| XRT7296IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTEGRATED LINE TRANSMITTER |
| XR-T7296IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/STS-1, E3 Integrated Line Transmitter |
| XRT7296IP-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7296IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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