參數(shù)資料
型號: XR-215ACP
廠商: EXAR CORP
元件分類: XO, clock
英文描述: Monolithic Phase-Locked Loop
中文描述: PLL FREQUENCY SYNTHESIZER, 25 MHz, PDIP16
封裝: 0.300 INCH, PLASTIC, DIP-16
文件頁數(shù): 24/32頁
文件大?。?/td> 331K
代理商: XR-215ACP
XR-215A
24
Rev. 1.01
8
16 V
CC
Figure 22. Circuit Connection For FSK Generation
U1
XR-215A
0.1 F
0.1 F
+12V
5K
5K
FSK Output
(Low Level)
2.5V
PP
F1
F2
FSK Output
10K
C
0
5K
R
x
Keying
Input
+5V
0V
0.1 F
3K
10K
10V
PP
F1
F2
Phase
Comp.
5
4
15
7
1
3
2
14
13
9
V
EE
10
12
11
6
VCO
Op
Amp
Frequency Synthesis
In frequency synthesis applications, a programmable counter or divide-by-N circuit is connected between the VCO
output (pin 15) and one of the phase detector inputs (pins 4 or 6), as shown in Figure 23. The principle of operation of the
circuit can be briefly explained as follows: The counter divides down the oscillator frequency by the programmable
divider modulus, N. Thus, when the entire system is phase-locked to an input signal at frequency, f
s
, the oscillator output
at pin 15 is at a frequency (Nf
s
), where N is the divider modulus. By proper choice of the divider modulus, a large number
of discrete frequencies can be synthesized from a given reference frequency. The low-pass filter capacitor C
1
is
normally chosen to provide a cut-off frequency equal to 0.1% to 2% of the signal frequency, f
s
.
相關(guān)PDF資料
PDF描述
XR215A Monolithic Phase-Locked Loop
XR-215A Monolithic Phase Locked Loop
XR-215 Monolithic Phase Locked Loop
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