參數(shù)資料
型號： XQV1000
廠商： Xilinx, Inc.
英文描述： QPRO Virtex 2.5V QML High-Reliability FPGAs(QPRO Virtex 2.5V QML 高可靠性現(xiàn)場可編程門陣列)
中文描述： QPRO的Virtex 2.5V的QML第高可靠性的FPGA（QPRO的Virtex 2.5V的QML第高可靠性現(xiàn)場可編程門陣列）
文件頁數(shù)： 1/28頁
文件大?。?/td> 287K
代理商： XQV1000
DS002 (v1.2) February 13, 2001
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
1
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
7
Features
Certified to MIL-PRF-38535 (Qualified Manufacturer
Listing)
Guaranteed over the full military temperature range
(–55
°
C to +125
°
C)
Ceramic and Plastic Packages
Fast, high-density Field-Programmable Gate Arrays
-
Densities from 100K to 1M system gates
-
System performance up to 200 MHz
-
Hot-swappable for Compact PCI
Multi-standard SelectI/O interfaces
-
16 high-performance interface standards
-
Connects directly to ZBTRAM devices
Built-in clock-management circuitry
-
Four dedicated delay-locked loops (DLLs) for
advanced clock control
-
Four primary low-skew global clock distribution
nets, plus 24 secondary global nets
Hierarchical memory system
-
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
-
Configurable synchronous dual-ported 4K-bit
RAMs
-
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
-
Dedicated carry logic for high-speed arithmetic
-
Dedicated multiplier support
-
Cascade chain for wide-input functions
-
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
-
Internal 3-state bussing
-
IEEE 1149.1 boundary-scan logic
-
Supported by FPGA Foundation and Alliance
Development Systems
-
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
-
Wide selection of PC and workstation platforms
SRAM-based in-system configuration
-
Unlimited reprogrammability
-
Four programming modes
0.22
μ
m 5-layer metal process
100% factory tested
Die-temperature sensing device
Description
The QPRO Virtex FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
exploiting an aggressive 5-layer-metal 0.22
μ
m CMOS pro-
cess. These advances make QPRO Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex family comprises the four members shown in
Table 1
.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the QPRO Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design flexibility while reducing time-to-market.
Refer to the
Arrays”
device architecture and timing specifications.
0
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