
QPRO XQ4000E/EX QML High-Reliability FPGAs
30
www.xilinx.com
1-800-255-7778
DS021 (v2.2) June 25, 2000
Product Specification
R
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
Symbol
Description
-4
Units
Min
Setup Times
T
PICK
T
PICKP
T
PICKD
T
PICKF
T
PICKFP
T
POCK
T
POCKP
Setup Times (TTL or CMOS Inputs)
Pad to Clock (IK), no delay
2.5
ns
Pad to Clock (IK), partial delay
10.8
ns
Pad to Clock (IK), full delay
15.7
ns
Pad to Clock (IK), via transparent Fast Capture Latch, no delay
3.9
ns
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay
12.3
ns
Pad to Fast Capture Latch Enable (OK), no delay
0.8
ns
Pad to Fast Capture Latch Enable (OK), partial delay
9.1
ns
T
ECIK
Clock Enable (EC) to Clock (IK)
0.3
ns
Hold Times
T
IKPI
T
IKPIP
T
IKPID
T
IKPIF
T
IKFPIP
T
IKFPID
T
IKEC
T
IKECP
T
IKECD
T
OKPI
T
OKPIP
Notes:
1.
For CMOS input levels, see the
"XQ4028EX Input Threshold Adjustments" on page 28
.
2.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on
page 28
.
Pad to Clock (IK), no delay
0
ns
Pad to Clock (IK), partial delay
0
ns
Pad to Clock (IK), full delay
0
ns
Pad to Clock (IK) via transparent Fast Capture Latch, no delay
0
ns
Pad to Clock (IK) via transparent Fast Capture Latch, partial delay
0
ns
Pad to Clock (IK) via transparent Fast Capture Latch, full delay
0
ns
Clock Enable (EC) to Clock (IK), no delay
0
ns
Clock Enable (EC) to Clock (IK), partial delay
0
ns
Clock Enable (EC) to Clock (IK), full delay
0
ns
Pad to Fast Capture Latch Enable (OK), no delay
0
ns
Pad to Fast Capture Latch Enable (OK), partial delay
0
ns