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參數(shù)資料
| 型號： | XQ4028E-3HQ196M |
| 廠商： | Xilinx, Inc. |
| 英文描述： | QML High-Reliability FPGAs |
| 中文描述： | QML第高可靠性的FPGA |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XQ4028E-3HQ196M |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
25
R
XQ4028EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
Symbol
Single Port RAM
Size
-4
Units
Min
Max
Write Operation
T
WC
T
WCT
T
WP
T
WPT
T
AS
T
AST
T
AH
T
AHT
T
DS
T
DST
T
DH
T
DHT
Address write cycle time
16x2
10.6
-
ns
32x1
10.6
-
ns
Write Enable pulse width (High)
16x2
5.3
-
ns
32x1
5.3
-
ns
Address setup time before WE
16x2
2.8
-
ns
32x1
2.8
-
ns
Address hold time after end of WE
16x2
1.7
-
ns
32x1
1.7
-
ns
DIN setup time before end of WE
16x2
1.1
-
ns
32x1
1.1
-
ns
DIN hold time after end of WE
16x2
6.6
-
ns
32x1
6.6
-
ns
Read Operation
T
RC
T
RCT
T
ILO
T
IHO
Address read cycle time
16x2
4.5
-
ns
32x1
6.5
-
ns
Data valid after address change (no Write Enable)
16x2
-
2.2
ns
32x1
-
3.8
ns
Read Operation, Clocking Data into Flip-Flop
T
ICK
T
IHCK
Address setup time before clock K
16x2
1.5
-
ns
32x1
3.2
-
ns
Read During Write
T
WO
T
WOT
T
DO
T
DOT
Data valid after WE goes active (DIN stable before WE)
16x2
-
6.5
ns
32x1
-
7.4
ns
Data valid after DIN (DIN changes during WE)
16x2
-
7.7
ns
32x1
-
8.2
ns
Read During Write, Clocking Data into Flip-Flop
T
WCK
T
WCKT
T
DCK
T
DOCK
WE setup time before clock K
16x2
7.1
-
ns
32x1
9.2
-
ns
Data setup time before clock K
16x2
5.9
-
ns
32x1
8.4
-
ns
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
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| XQ4028E-3HQ196N | QML High-Reliability FPGAs |
| XQ4028E-3PG196M | QML High-Reliability FPGAs |
| XQ4028E-3PG196N | QML High-Reliability FPGAs |
| XQ4028E-4BG196M | QML High-Reliability FPGAs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4028E-3HQ196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4028E-3PG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4028E-3PG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QPRO XQ4000E/EX QML High-Reliability FPGAs |
| XQ4028E-3PG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4028E-3PG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
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