
QPRO XQ4000E/EX QML High-Reliability FPGAs
26
www.xilinx.com
1-800-255-7778
DS021 (v2.2) June 25, 2000
Product Specification
R
XQ4028EX CLB Level-Sensitive RAM Timing Waveforms
Figure 1:
DS021_03_060100
WE
ADDRESS
WRITE
READ WITHOUT WRITE
READ, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
READ DURING WRITE
DATA IN
CLOCK
XQ,YQ OUTPUTS
WRITE ENABLE
DATA IN
(stable during WE)
WRITE ENABLE
DATA IN
CLOCK
DATA IN
(changing during WE)
X,Y OUTPUTS
VALID
VALID
OLD
NEW
VALID
VALID (NEW)
VALID (OLD)
VALID
T
AS
T
ILO
T
AH
T
DS
REQUIRED
T
DH
T
WP
T
WC
T
ICK
T
CH
T
CKO
X,Y OUTPUTS
X,Y OUTPUTS
XQ,YQ OUTPUTS
T
DH
T
WO
T
WO
T
DO
T
WCK
T
DCK
T
CKO
T
WP
T
WP
VALID
(OLD)
VALID
(PREVIOUS)
VALID
(NEW)