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參數(shù)資料
| 型號(hào)： | XPS16550 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | PLB v4.6 based PLB interface |
| 中文描述： | 基于小巴小巴v4.6界面 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大小： | 441K |
| 代理商： | XPS16550 |
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DS577 April 18, 2007
Product Specification
www.xilinx.com
1
2006=2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at
http://www.xilinx.com/legal.htm
. All other trademarks
and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application,
or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implemen-
tation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this imple-
mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
Introduction
This document provides the specification for the XPS
16550
UART
(Universal
Receiver/Transmitter) Intellectual Property (IP).
Asynchronous
The
XPS 16550 UART
described in this document has
been incorporating features described in
National
Semiconductor PC16550D UART with FIFOs
data sheet
.
The National Semiconductor PC16550D
data sheet
is
referenced throughout this document and should be
used as the authoritative specification. Differences
between the National Semiconductor PC16550D and
the XPS 16550 UART are highlighted in
Specification
Exceptions
section.
Features
PLB v4.6 based PLB interface
Hardware and software register compatible with all
standard 16450 and 16550 UARTs
Implements all standard serial interface protocols
- 5, 6, 7 or 8 bits per character
- Odd, Even or no parity detection and generation
- 1, 1.5 or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver
clock input
- Modem control functions
- Prioritized transmit, receive, line status and
modem control interrupts
- False start bit detection and recover
- Line break detection and generation
- Internal loop back diagnostic functionality
- Independent 16 word transmit and receive FIFOs
0
XPS 16550 UART (v1.00a)
DS577 April 20, 2007
0
0
Product Specification
LogiCORE Facts
Core Specifics
Supported Device
Family
Spartan-3E, Spartan-3,
Spartan-3A, Spartan-3AN,
Virtex-4 and Virtex-5
Version of Core
xps_uart16550
v1.00a
Resources Used
Min
Max
Slices
Refer to the
Table 17
,
Table 18
and
Table 19
LUTs
FFs
Block RAMs
N/A
Special Features
N/A
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs &
Application notes
N/A
Additional Items
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE 9.1i or later
Verification
Modelsim SE /EE6.0c or later
Simulation
ModelSim SE/EE 6.0c or later
Synthesis
XST 9.1i or later
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