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參數(shù)資料
| 型號： | XPC823CZT66B2T |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 23 X 23 MM, 1.27 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 2/81頁 |
| 文件大?。?/td> | 580K |
| 代理商： | XPC823CZT66B2T |
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10
MPC823 ELECTRICAL SPECIFICATIONS
MOTOROLA
B40
A(6:31), TSIZ(0:1), RD/WR, BURST, Valid to CLKOUT Rising
Edge
977
ns
B41
TS Valid to CLKOUT Rising Edge (Setup Time)
977
ns
B42
CLKOUT Rising Edge to TS Valid (Hold Time)
222
ns
B43
AS Negation to Memory Controller Signals Negation
13
13
13
ns
NOTES:
1.
The timing for BR output is relevant when the MPC823 is selected to work with the external bus arbiter.
The timing for BG output is relevant when the MPC823 is selected to work with the internal bus arbiter.
2.
The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device
(and not when the memory controller or the PCMCIA interface drive them).
3.
The timing required for BR input is relevant when the MPC823 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC823 is selected to work with the external bus arbiter.
4.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA
input signal is asserted.
5.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is
valid only under control of the UPM in the memory controller.
6.
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
7.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings
specied in B37 and B38 are specied to enable the freeze of the UPM output signals.
8.
The AS signal is considered asynchronous to the CLKOUT signal.
Figure 1. External Clock Timing Diagram
Table 1. Bus Operation Timing (Continued)
NUM
CHARACTERISTIC
25MHz
40MHz
50MHz
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
CLKOUT
B1
B4
B5
B3
B2
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