參數(shù)資料
型號(hào)： XE1202
廠商： Electronic Theatre Controls, Inc.
英文描述： Low-power, integrated UHF transceiver
中文描述： 低功耗，超高頻收發(fā)器集成
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 451K
代理商： XE1202
Data Sheet
XE1202
Symbol
Description
Conditions
A-mode,low range:
VTHR1
Min
-
-
-
-
-
Typ
Max
-
-
-
-
-
Unit
dBm
dBm
dBm
dBm
dBm
dBm
VTHR
Equivalent input thresholds
of the RSSI
VTHR2
VTHR3
A-mode,high range:
VTHR1
VTHR2
VTHR3
-
-105
-100
-95
-90
-85
-80
-
FERR
Error threshold for the FEI
Pw=-100 dBm, A-mode
RTParam_Fsel = 1
-
0.5
-
-
SPR
Spurious emission in receiver
mode
-
-55
-50
dBm
VIH
Digital input level high
in % VDD
75
-
-
%
VIL
Digital input level low
in % VDD
-
-
25
%
VOH
Digital output level high
in % VDD
75
-
-
%
VOL
Digital output level low
in % VDD
-
-
25
%
4 Description
The XE1202 is a direct conversion (0-IF) half-duplex data transceiver. It includes a receiver, a transmitter, a
frequency synthesizer and some service blocks. The circuit operates in 3 frequency ranges (433MHz, 868MHz,
915MHz) and uses 2-level FSK modulation.
In a typical application, the XE1202 is programmed by a microcontroller through the 3-wire serial bus SI, SO, SCK
to write to and read from the configuration registers.
The circuit consists of 4 main functional blocks:
The receiver
converts the incoming 2-level FSK modulated signal into a synchronized bit stream. The receiver is
composed of a low-noise amplifier, down-conversion mixers, baseband filters, baseband amplifiers, limiters,
demodulator and the bit synchronizer. The bit synchronizer transforms the data output of the demodulator into a
glitch-free bit stream DATAOUT and generates a synchronized clock DCLK to be used to easily sample the
DATAOUT signal without loading an external processor with heavy signal processing. In addition, the receiver
includes a Received Signal Strength Indicator function (RSSI), a Frequency Error Indicator function (FEI) that gives
indication about the frequency error of the local oscillator, and pattern recognition function to detect programmable
reference word in the incoming bit stream. The bandwidth of the base-band filters, the frequency deviation of the
expected incoming FSK signal as well as the bitrate of this bit stream are programmable.
The transmitter
performs the modulation of the carrier by an input bit stream and the transmission of the
modulated signal. The modulation is made directly through the frequency synthesizer. An on-chip power amplifier
then amplifies the signal. The output power is programmable among 4 possible values. The frequency deviation
and the bit rate for the transmit signal are the same as those programmed for the receiver section.
The frequency synthesizer
generates the local oscillator (LO) signal for the receiver section as well as the FSK
modulated signal for the transmitter section. The core of the synthesizer is implemented with a PLL structure. The
frequency is programmable with a step of 500 Hz in 3 frequency bands, 433-, 868-, and 915-MHz. This section
includes a crystal oscillator whose signal is the reference for the PLL. This reference frequency is divided by 4, 8,
16, or 32 and is made available at the CLKOUT pin to serve as a clock signal for an external processor.
The control block
generates the control signals according to the setting in its set of configuration registers.
The service block
performs all the necessary functions for the circuit to work properly, including the internal
voltage and current sources.
7
D0211-105
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