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| 型號： | XCV405E-7FG676C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 69/118頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 10800 |
| RAM 位總計： | 573440 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 129600 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應商設(shè)備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
50
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
VHDL Instantiation
data0_p:
IOBUF_LVDS port map
(I=>data_out(0), T=>data_tri,
IO=>data_p(0), O=>data_int(0));
data0_inv: INV
port map
(I=>data_out(0),
O=>data_n_out(0));
data0_n
: IOBUF_LVDS port map
(I=>data_n_out(0), T=>data_tri,
IO=>data_n(0), O=>open);
Verilog Instantiation
IOBUF_LVDS data0_p(.I(data_out[0]),
.T(data_tri), .IO(data_p[0]),
.O(data_int[0]);
INV
data0_inv (.I(data_out[0],
.O(data_n_out[0]);
IOBUF_LVDS
data0_n(.I(data_n_out[0]),.T(data_tri),.
IO(data_n[0]).O());
Location Constraints
All LVDS buffers must be explicitly placed on a device. For
the output buffers this can be done with the following con-
straint in the UCF or NCF file.
NET data_p<0> LOC = D28; # IO_L0P
NET data_n<0> LOC = B29; # IO_L0N
Synchronous vs. Asynchronous Bidirectional
Buffers
If the output side of the bidirectional buffers are synchro-
nous (registered in the IOB), then any IO_L#P|N pair can be
used. If the output side of the bidirectional buffers are asyn-
chronous (no output register), then they must use one of the
pairs that is a part of the asynchronous LVDS IOB group.
This applies for either the 3-state pin or the data out pin.
The LVDS pairs that can be used as asynchronous bidirec-
tional buffers are listed in the Virtex-E pinout tables. Some
pairs are marked as asynchronous capable for all devices in
that package, and others are marked as available only for
that device in the package. If the device size might change
at some point in the product’s lifetime, then only the com-
mon pairs for all packages should be used.
Adding Output and 3-State Registers
All LVDS buffers can have output and input registers in the
IOB. The output registers must be in both the P-side and
N-side IOBs, the input register is only in the P-side. All the
normal IOB register options are available (FD, FDE, FDC,
FDCE, FDP, FDPE, FDR, FDRE, FDS, FDSE, LD, LDE,
LDC, LDCE, LDP, LDPE). The register elements can be
inferred or explicitly instantiated in the HDL code. Special
care must be taken to insure that the D pins of the registers
are inverted and that the INIT states of the registers are
opposite. The 3-state (T), 3-state clock enable (CE), clock
pin (C), output clock enable (CE), and set/reset (CLR/PRE
or S/R) pins must connect to the same source. Failure to do
this leads to a DRC error in the software.
The register elements can be packed in the IOB using the
IOB property to TRUE on the register or by using the “map
-pr [i|o|b]”, where “i” is inputs only, “o” is outputs only, and “b”
is both inputs and outputs. To improve design coding times,
VHDL and Verilog synthesis macro libraries have been
developed to explicitly create these structures. The bidirec-
tional I/O library macros are listed in Table 44.
The 3-state is configured to be 3-stated at GSR and when
the PRE, CLR, S, or R is asserted and shares its clock
enable with the output and input register. If this is not desir-
able, then the library can be updated with the desired func-
tionality by the user. The I/O and IOB inputs to the macros
are the external net connections.
Table 44:
Bidirectional I/O Library Macros
Name
Inputs
Bidirectional
Outputs
IOBUFDS_FD_LVDS
D, T, C
IO, IOB
Q
IOBUFDS_FDE_LVDS
D, T, CE, C
IO, IOB
Q
IOBUFDS_FDC_LVDS
D, T, C, CLR
IO, IOB
Q
IOBUFDS_FDCE_LVDS
D, T, CE, C, CLR
IO, IOB
Q
IOBUFDS_FDP_LVDS
D, T, C, PRE
IO, IOB
Q
IOBUFDS_FDPE_LVDS
D, T, CE, C, PRE
IO, IOB
Q
IOBUFDS_FDR_LVDS
D, T, C, R
IO, IOB
Q
IOBUFDS_FDRE_LVDS
D, T, CE, C, R
IO, IOB
Q
IOBUFDS_FDS_LVDS
D, T, C, S
IO, IOB
Q
IOBUFDS_FDSE_LVDS
D, T, CE, C, S
IO, IOB
Q
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-7FG676I | 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-7FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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