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參數(shù)資料
| 型號： | XCV2000E-8FG680C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 158/233頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 680-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 9600 |
| 邏輯元件/單元數(shù)： | 43200 |
| RAM 位總計： | 655360 |
| 輸入/輸出數(shù)： | 512 |
| 門數(shù)： | 2541952 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 680-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 680-FBGA（40x40） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
24
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Because any single DLL can access only two BUFGs at
most, any additional output clock signals must be routed
from the DLL in this example on the high speed backbone
routing.
The dll_2x files in the xapp132.zip file show the VHDL and
Verilog implementation of this circuit.
Virtex-E 4x Clock
Two DLLs located in the same half-edge (top-left, top-right,
bottom-right, bottom-left) can be connected together, with-
out using a BUFG between the CLKDLLs, to generate a 4x
clock as shown in Figure 30. Virtex-E devices, like the Virtex
devices, have four clock networks that are available for inter-
nal deskewing of the clock. Each of the eight DLLs have
access to two of the four clock networks. Although all the
DLLs can be used for internal deskewing, the presence of
two GCLKBUFs on the top and two on the bottom indicate
that only two of the four DLLs on the top (and two of the four
DLLs on the bottom) can be used for this purpose.
The dll_4xe files in the xapp132.zip file show the DLL imple-
mentation in Verilog for Virtex-E devices. These files can be
found at:
Using Block SelectRAM+ Features
The Virtex FPGA Series provides dedicated blocks of
on-chip, true dual-read/write port synchronous RAM, with
4096 memory cells. Each port of the block SelectRAM+
memory can be independently configured as a read/write
port, a read port, a write port, and can be configured to a
specific data width. The block SelectRAM+ memory offers
new capabilities allowing the FPGA designer to simplify
designs.
Operating Modes
VIrtex-E block SelectRAM+ memory supports two operating
modes:
Read Through
Write Back
Read Through (one clock edge)
The read address is registered on the read port clock edge
and data appears on the output after the RAM access time.
Some memories might place the latch/register at the out-
puts, depending on whether a faster clock-to-out versus
set-up time is desired. This is generally considered to be an
inferior solution, since it changes the read operation to an
asynchronous function with the possibility of missing an
address/control line transition during the generation of the
read pulse clock.
Write Back (one clock edge)
The write address is registered on the write port clock edge
and the data input is written to the memory and mirrored on
the output.
Block SelectRAM+ Characteristics
All inputs are registered with the port clock and have a
set-up to clock timing specification.
All outputs have a read through or write back function
depending on the state of the port WE pin. The outputs
relative to the port clock are available after the
clock-to-out timing specification.
The block SelectRAMs are true SRAM memories and
do not have a combinatorial path from the address to
the output. The LUT SelectRAM+ cells in the CLBs are
still available with this function.
The ports are completely independent from each other
(i.e., clocking, control, address, read/write function, and
data width) without arbitration.
A write operation requires only one clock edge.
A read operation requires only one clock edge.
The output ports are latched with a self timed circuit to guar-
antee a glitch free read. The state of the output port does
not change until the port executes another read or write
operation.
Library Primitives
SelectRAM+ primitives. Table 14 describes all of the avail-
able primitives for synthesis and simulation.
Figure 30: DLL Generation of 4x Clock in Virtex-E
Devices
ds022_031_041901
RST
CLKFB
CLKIN
CLKDLL-S
LOCKED
CLKDV
INV
BUFG
OBUF
IBUFG
CLK2X
CLK0
CLK90
CLK180
CLK270
RST
CLKFB
CLKIN
CLKDLL-P
LOCKED
CLKDV
CLK2X
CLK0
CLK90
CLK180
CLK270
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| XCV2000E-7FG680I | IC FPGA 1.8V I-TEMP 680-FBGA |
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| ASM43DTMD | CONN EDGECARD 86POS R/A .156 SLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV2000E-8FG680I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV2000E-8FG860C | 功能描述:IC FPGA 1.8V C-TEMP 860-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV2000E-8FG860I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV2000E-8HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV2000E-8HQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
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