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參數(shù)資料
| 型號： | XCV100E |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 87K |
| 代理商： | XCV100E |
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Features
Fast, High-Density 1.8 V FPGA Family
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Densities from 58 k to 4 M system gates
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130 MHz internal performance (four LUT levels)
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Designed for low-power operation
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PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Highly Flexible SelectI/O+ Technology
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Supports 20 high-performance interface standards
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Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
Differential Signalling Support
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LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
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Differential I/O signals can be input, output, or I/O
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Compatible with standard differential devices
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LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink
Technology
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Double Data Rate (DDR) to Virtex-E link
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Web-based HDL generation methodology
Sophisticated SelectRAM+ Memory Hierarchy
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1 Mb of internal configurable distributed RAM
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Up to 832 Kb of synchronous internal block RAM
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True Dual-Port BlockRAM capability
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Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
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Designed for high-performance Interfaces to
External Memories
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200 MHz ZBT* SRAMs
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200 Mb/s DDR SDRAMs
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Supported by free Synthesizable reference design
High-Performance Built-In Clock Management Circuitry
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Eight fully digital Delay-Locked Loops (DLLs)
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Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
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Clock Multiply and Divide
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Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Flexible Architecture Balances Speed and Density
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Dedicated carry logic for high-speed arithmetic
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Dedicated multiplier support
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Cascade chain for wide-input function
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Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
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Internal 3-state bussing
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IEEE 1149.1 boundary-scan logic
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Die-temperature sensor diode
Supported by Xilinx Foundation and Alliance Series
Development Systems
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Further compile time reduction of 50%
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Internet Team Design (ITD) tool ideal for
million-plus gate density designs
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Wide selection of PC and workstation platforms
SRAM-Based In-System Configuration
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Unlimited re-programmability
Advanced Packaging Options
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0.8 mm Chip-scale
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1.0 mm BGA
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1.27 mm BGA
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HQ/PQ
0.18
m
m 6-Layer Metal Process
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
0
Virtex-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
0
0
Preliminary Product Specification
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV100E-6BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-6BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV100E-6BG352C | 功能描述:IC FPGA 1.8V 128K GATES 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 標準包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計:2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應商設備封裝:676-FBGA（27x27） |
| XCV100E-6BG352I | 功能描述:IC FPGA 1.8V I-TEMP 352-MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV100E-6BG352I0773 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
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