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| 型號： | XCS40XL-5VQ256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 8/82頁 |
| 文件大小： | 863K |
| 代理商： | XCS40XL-5VQ256I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
16
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
CLB signals from which they are originally derived are
shown in Table 10.
The RAM16X1D primitive used to instantiate the dual-port
RAM consists of an upper and a lower 16 x 1 memory array.
The address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 single-port RAM array described
previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO) serves
as the data output for the upper memory. Therefore, DPO
reflects the data at address DPRA[3:0].
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO that
can read and write simultaneously is easily generated. The
simultaneous
read/write
capability
possible
with
the
dual-port RAM can provide twice the effective data through-
put of a single-port RAM alternating read and write opera-
tions.
The timing relationships for the dual-port RAM mode are
shown in Figure 13.
Note that write operations to RAM are synchronous
(edge-triggered); however, data access is asynchronous.
Initializing RAM at FPGA Configuration
Both RAM and ROM implementations in the Spartan/XL
families are initialized during device configuration. The initial
contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents are
initialized to zeros, by default.
RAM initialization occurs only during device configuration.
The RAM content is not affected by GSR.
More Information on Using RAM Inside CLBs
Three application notes are available from Xilinx that dis-
cuss synchronous (edge-triggered) RAM: "Xilinx Edge-Trig-
gered and Dual-Port RAM Capability," "Implementing FIFOs
in Xilinx RAM," and "Synchronous and Asynchronous FIFO
Designs." All three application notes apply to both the Spar-
tan and the Spartan-XL families.
Fast Carry Logic
Each CLB F-LUT and G-LUT contains dedicated arithmetic
logic for the fast generation of carry and borrow signals.
This extra output is passed on to the function generator in
the adjacent CLB. The carry chain is independent of normal
routing resources. (See Figure 15.)
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry gen-
erate/propagate are meaningless even at the 16-bit level,
and of marginal benefit at the 32-bit level. This fast carry
logic is one of the more significant features of the Spartan
Table 10: Dual-Port RAM Signals
RAM Signal
Function
CLB Signal
DData In
DIN
A[3:0]
Read Address for
Single-Port.
Write Address for
Single-Port and
Dual-Port.
F[4:1]
DPRA[3:0]
Read Address for
Dual-Port
G[4:1]
WE
Write Enable
SR
WCLK
Clock
K
SPO
Single Port Out
(addressed by A[3:0])
FOUT
DPO
Dual Port Out
(addressed by
DPRA[3:0])
GOUT
Figure 15: Available Spartan/XL Carry Propagation
Paths
CLB
DS060_15_081100
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