參數(shù)資料
型號(hào)： XCS40XL-5CS280C
廠商： XILINX INC
元件分類： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 784 CLBS, 13000 GATES, 250 MHz, PBGA280
封裝： CSP-280
文件頁(yè)數(shù)： 58/83頁(yè)
文件大小： 770K
代理商： XCS40XL-5CS280C
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v1.8) June 26, 2008
61
Product Specification
R
Spartan-XL Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
Symbol
Description
Device
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Propagation Delays
TOKPOF
Clock (OK) to Pad, fast
All devices
-
3.2
-
3.7
ns
TOPF
Output (O) to Pad, fast
All devices
-
2.5
-
2.9
ns
TTSHZ
3-state to Pad High-Z (slew-rate independent)
All devices
-
2.8
-
3.3
ns
TTSONF
3-state to Pad active and valid, fast
All devices
-
2.6
-
3.0
ns
TOFPF
Output (O) to Pad via Output Mux, fast
All devices
-
3.7
-
4.4
ns
TOKFPF
Select (OK) to Pad via Output Mux, fast
All devices
-
3.3
-
3.9
ns
TSLOW
For Output SLOW option add
All devices
-
1.5
-
1.7
ns
Setup and Hold Times
TOOK
Output (O) to clock (OK) setup time
All devices
0.5
-
0.5
-
ns
TOKO
Output (O) to clock (OK) hold time
All devices
0.0
-
0.0
-
ns
TECOK
Clock Enable (EC) to clock (OK) setup time
All devices
0.0
-
0.0
-
ns
TOKEC
Clock Enable (EC) to clock (OK) hold time
All devices
0.1
-
0.2
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
10.5
-
11.5
-
ns
TRPO
Delay from GSR input to any Pad
XCS05XL
-
11.9
-
14.0
ns
XCS10XL
-
12.4
-
14.5
ns
XCS20XL
-
12.9
-
15.0
ns
XCS30XL
-
13.9
-
16.0
ns
XCS40XL
-
14.9
-
17.0
ns
Notes:
1.
Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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