參數(shù)資料
型號: XCS40XL-4PQ240C
廠商: Xilinx Inc
文件頁數(shù): 44/83頁
文件大小: 0K
描述: IC 3.3V FPGA COMM. TEMP 240PQFP
產品變化通告: Product Discontinuation 26/Oct/2011
標準包裝: 24
系列: Spartan®-XL
LAB/CLB數(shù): 784
邏輯元件/單元數(shù): 1862
RAM 位總計: 25088
輸入/輸出數(shù): 192
門數(shù): 40000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 240-BFQFP
供應商設備封裝: 240-PQFP(32x32)
其它名稱: Q1039179A
Q1150517
XCS40XL4PQ240C
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
49
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading.
Spartan Family Primary and Secondary Setup and Hold
Symbol
Description
Device
Speed Grade
Units
-4
-3
Min
Input Setup/Hold Times Using Primary Clock and IFF
TPSUF/TPHF
No Delay
XCS05
1.2 / 1.7
1.8 / 2.5
ns
XCS10
1.0 / 2.3
1.5 / 3.4
ns
XCS20
0.8 / 2.7
1.2 / 4.0
ns
XCS30
0.6 / 3.0
0.9 / 4.5
ns
XCS40
0.4 / 3.5
0.6 / 5.2
ns
TPSU/TPH
With Delay
XCS05
4.3 / 0.0
6.0 / 0.0
ns
XCS10
4.3 / 0.0
6.0 / 0.0
ns
XCS20
4.3 / 0.0
6.0 / 0.0
ns
XCS30
4.3 / 0.0
6.0 / 0.0
ns
XCS40
5.3 / 0.0
6.8 / 0.0
ns
Input Setup/Hold Times Using Secondary Clock and IFF
TSSUF/TSHF
No Delay
XCS05
0.9 / 2.2
1.5 / 3.0
ns
XCS10
0.7 / 2.8
1.2 / 3.9
ns
XCS20
0.5 / 3.2
0.9 / 4.5
ns
XCS30
0.3 / 3.5
0.6 / 5.0
ns
XCS40
0.1 / 4.0
0.3 / 5.7
ns
TSSU/TSH
With Delay
XCS05
4.0 / 0.0
5.7 / 0.0
ns
XCS10
4.0 / 0.0
5.7 / 0.0
ns
XCS20
4.0 / 0.5
5.7 / 0.5
ns
XCS30
4.0 / 0.5
5.7 / 0.5
ns
XCS40
5.0 / 0.0
6.5 / 0.0
ns
Notes:
1.
Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
2.
IFF = Input Flip-flop or Latch
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