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參數資料
| 型號： | XCS40-5BG208I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現場可編程門陣列 |
| 文件頁數： | 54/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS40-5BG208I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
54
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Spartan-XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
T
GLS
Description
Device
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Speed Grade
-5
Max
1.4
1.7
2.0
2.3
2.6
Units
ns
ns
ns
ns
ns
-4
Max
1.5
1.8
2.1
2.5
2.8
From pad through buffer, to any clock K
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| XCS40-5BG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS40-5BG280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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