參數(shù)資料
型號(hào)： XCS40-4PQ208C
廠商： XILINX INC
元件分類(lèi)： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 784 CLBS, 13000 GATES, 166 MHz, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 42/83頁(yè)
文件大?。?/td> 770K
代理商： XCS40-4PQ208C
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v1.8) June 26, 2008
47
Product Specification
R
Spartan Family Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Pin-to-pin timing
parameters are derived from measuring external and inter-
nal test patterns and are guaranteed over worst-case oper-
ating conditions (supply voltage and junction temperature).
Listed below are representative values for typical pin loca-
tions and normal clock loading. For more specific, more pre-
cise, and worst-case guaranteed data, reflecting the actual
routing structure, use the values provided by the static tim-
ing analyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report.
Spartan Family Output Flip-Flop, Clock-to-Out
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
Global Primary Clock to TTL Output using OFF
TICKOF
Fast
XCS05
5.3
8.7
ns
XCS10
5.7
9.1
ns
XCS20
6.1
9.3
ns
XCS30
6.5
9.4
ns
XCS40
6.8
10.2
ns
TICKO
Slew-rate limited
XCS05
9.0
11.5
ns
XCS10
9.4
12.0
ns
XCS20
9.8
12.2
ns
XCS30
10.2
12.8
ns
XCS40
10.5
12.8
ns
Global Secondary Clock to TTL Output using OFF
TICKSOF
Fast
XCS05
5.8
9.2
ns
XCS10
6.2
9.6
ns
XCS20
6.6
9.8
ns
XCS30
7.0
9.9
ns
XCS40
7.3
10.7
ns
TICKSO
Slew-rate limited
XCS05
9.5
12.0
ns
XCS10
9.9
12.5
ns
XCS20
10.3
12.7
ns
XCS30
10.7
13.2
ns
XCS40
11.0
14.3
ns
Delay Adder for CMOS Outputs Option
TCMOSOF Fast
All devices
0.8
1.0
ns
TCMOSO
Slew-rate limited
All devices
1.5
2.0
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 33.
3.
OFF = Output Flip-Flop
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