參數資料
| 型號： | XCS30XL-4PQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 27/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP HP 240PQFP |
| 產品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標準包裝： | 24 |
| 系列： | Spartan®-XL |
| LAB/CLB數： | 576 |
| 邏輯元件/單元數： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數： | 192 |
| 門數： | 30000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
33
Product Specification
R
Product Obsolete/Under Obsolescence
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 29. The checksum consists of the 11 most signifi-
cant bits of the 16-bit code. A change in the checksum indi-
cates a change in the Readback bitstream. A comparison to
a previous checksum is meaningful only if the readback
data is independent of the current device state. CLB outputs
should not be included (Readback Capture option not
used), and if RAM is present, the RAM content must be
unchanged.
Statistically, one error out of 2048 might go undetected.
Table 17: Spartan/XL Program Data
Device
XCS05
XCS10
XCS20
XCS30
XCS40
Max System
Gates
5,000
10,000
20,000
30,000
40,000
CLBs
(Row x Col.)
100
(10 x 10)
196
(14 x 14)
400
(20 x 20)
576
(24 x 24)
784
(28 x 28)
IOBs
80
112
160
192
205(4)
Part Number
XCS05 XCS05XL XCS10 XCS10XL XCS20 XCS20XL XCS30 XCS30XL XCS40 XCS40XL
Supply Voltage
5V
3.3V5V
3.3V5V3.3V
5V3.3V5V3.3V
Bits per Frame
126
127
166
167
226
227
266
267
306
307
Frames
428
429
572
573
788
789
932
933
1,076
1,077
Program Data
53,936
54,491
94,960
95,699
178,096
179,111
247,920
249,119
329,264
330,647
PROM Size
(bits)
53,984
54,544
95,008
95,752
178,144
179,160
247,968
249,168
329,312
330,696
Express Mode
PROM Size
(bits)
-
79,072
-
128,488
-
221,056
-
298,696
-
387,856
Notes:
1.
Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+1 for Spartan-XL
device)
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device)
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte
2.
The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame,
following the four error check bits. However, the Length Count value must be adjusted for all such extra "one" bits, even for extra
leading ones at the beginning of the header.
3.
Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + additional start-up bits.
4.
XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
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| XCS30XL-4PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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| XCS30XL-4PQ280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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