參數(shù)資料
型號(hào)： XCS30XL-4CS280C
廠商： XILINX INC
元件分類： FPGA
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： FPGA, 576 CLBS, 10000 GATES, 217 MHz, PBGA280
封裝： CSP-280
文件頁(yè)數(shù)： 40/83頁(yè)
文件大?。?/td> 770K
代理商： XCS30XL-4CS280C
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v1.8) June 26, 2008
45
Product Specification
R
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
Symbol
Single Port RAM
Size(1)
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Write Operation
TWCS
Address write cycle time (clock K period)
16x2
8.0
-
11.6
-
ns
TWCTS
32x1
8.0
-
11.6
-
ns
TWPS
Clock K pulse width (active edge)
16x2
4.0
-
5.8
-
ns
TWPTS
32x1
4.0
-
5.8
-
ns
TASS
Address setup time before clock K
16x2
1.5
-
2.0
-
ns
TASTS
32x1
1.5
-
2.0
-
ns
TAHS
Address hold time after clock K
16x2
0.0
-
0.0
-
ns
TAHTS
32x1
0.0
-
0.0
-
ns
TDSS
DIN setup time before clock K
16x2
1.5
-
2.7
-
ns
TDSTS
32x1
1.5
-
1.7
-
ns
TDHS
DIN hold time after clock K
16x2
0.0
-
0.0
-
ns
TDHTS
32x1
0.0
-
0.0
-
ns
TWSS
WE setup time before clock K
16x2
1.5
-
1.6
-
ns
TWSTS
32x1
1.5
-
1.6
-
ns
TWHS
WE hold time after clock K
16x2
0.0
-
0.0
-
ns
TWHTS
32x1
0.0
-
0.0
-
ns
TWOS
Data valid after clock K
16x2
-
6.5
-
7.9
ns
TWOTS
32x1
-
7.0
-
9.3
ns
Read Operation
TRC
Address read cycle time
16x2
2.6
-
2.6
-
ns
TRCT
32x1
3.8
-
3.8
-
ns
TILO
Data valid after address change (no Write
Enable)
16x2
-
1.2
-
1.6
ns
TIHO
32x1
-
2.0
-
2.7
ns
TICK
Address setup time before clock K
16x2
1.8
-
2.4
-
ns
TIHCK
32x1
2.9
-
3.9
-
ns
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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