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參數資料
| 型號： | XCS30-4PQ208C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 166 MHz, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數： | 57/83頁 |
| 文件大?。?/td> | 770K |
| 代理商： | XCS30-4PQ208C |
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Spartan and Spartan-XL FPGA Families Data Sheet
60
DS060 (v1.8) June 26, 2008
Product Specification
R
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Symbol
Device
Speed Grade
Units
-5
-4
Description
Min
Max
Min
Max
Setup Times
TECIK
Clock Enable (EC) to Clock (IK)
All devices
0.0
-
0.0
-
ns
TPICK
Pad to Clock (IK), no delay
All devices
1.0
-
1.2
-
ns
TPOCK
Pad to Fast Capture Latch Enable (OK), no delay
All devices
0.7
-
0.8
-
ns
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
TPID
Pad to I1, I2
All devices
-
0.9
-
1.1
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.1
-
2.5
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
All devices
-
1.0
-
1.1
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
1.1
-
1.2
ns
Delay Adder for Input with Full Delay Option
TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05XL
4.0
-
4.7
-
ns
XCS10XL
4.8
-
5.6
-
ns
XCS20XL
5.0
-
5.9
-
ns
XCS30XL
5.5
-
6.5
-
ns
XCS40XL
6.5
-
7.6
-
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
All devices
10.5
-
11.5
-
ns
TRRI
Delay from GSR input to any Q
XCS05XL
-
9.0
-
10.5
ns
XCS10XL
-
9.5
-
11.0
ns
XCS20XL
-
10.0
-
11.5
ns
XCS30XL
-
11.0
-
12.5
ns
XCS40XL
-
12.0
-
13.5
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XCS30-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:Spartan® 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，FCBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-4PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-4PQ256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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