參數(shù)資料
型號(hào)： XCS30-3TQ144C
廠商： Xilinx Inc
文件頁數(shù)： 52/83頁
文件大小： 0K
描述： IC FPGA 5V C-TEMP 144-TQFP
產(chǎn)品變化通告： Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 113
門數(shù)： 30000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
Spartan and Spartan-XL FPGA Families Data Sheet
56
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
Symbol
Single Port RAM
Size(1)
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Write Operation
TWCS
Address write cycle time (clock K period)
16x2
7.7
-
8.4
-
ns
TWCTS
32x1
7.7
-
8.4
-
ns
TWPS
Clock K pulse width (active edge)
16x2
3.1
-
3.6
-
ns
TWPTS
32x1
3.1
-
3.6
-
ns
TASS
Address setup time before clock K
16x2
1.3
-
1.5
-
ns
TASTS
32x1
1.5
-
1.7
-
ns
TDSS
DIN setup time before clock K
16x2
1.5
-
1.7
-
ns
TDSTS
32x1
1.8
-
2.1
-
ns
TWSS
WE setup time before clock K
16x2
1.4
-
1.6
-
ns
TWSTS
32x1
1.3
-
1.5
-
ns
All hold times after clock K
16x2
0.0
-
0.0
-
ns
TWOS
Data valid after clock K
32x1
-
4.5
-
5.3
ns
TWOTS
16x2
-
5.4
-
6.3
ns
Read Operation
TRC
Address read cycle time
16x2
2.6
-
3.1
-
ns
TRCT
32x1
3.8
-
5.5
-
ns
TILO
Data Valid after address change (no Write
Enable)
16x2
-
1.0
-
1.1
ns
TIHO
32x1
-
1.7
-
2.0
ns
TICK
Address setup time before clock K
16x2
0.6
-
0.7
-
ns
TIHCK
32x1
1.3
-
1.6
-
ns
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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參數(shù)描述
XCS30-3TQ144I 功能描述:IC FPGA 5V I-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789
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