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| 型號： | XCS20-5BG84I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 40/82頁 |
| 文件大?。?/td> | 863K |
| 代理商： | XCS20-5BG84I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and are expressed in nanosec-
onds unless otherwise noted.
Symbol
Single Port RAM
Size(1)
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Write Operation
TWCS
Address write cycle time (clock K period)
16x2
8.0
-
11.6
-
ns
TWCTS
32x1
8.0
-
11.6
-
ns
TWPS
Clock K pulse width (active edge)
16x2
4.0
-
5.8
-
ns
TWPTS
32x1
4.0
-
5.8
-
ns
TASS
Address setup time before clock K
16x2
1.5
-
2.0
-
ns
TASTS
32x1
1.5
-
2.0
-
ns
TAHS
Address hold time after clock K
16x2
0.0
-
0.0
-
ns
TAHTS
32x1
0.0
-
0.0
-
ns
TDSS
DIN setup time before clock K
16x2
1.5
-
2.7
-
ns
TDSTS
32x1
1.5
-
1.7
-
ns
TDHS
DIN hold time after clock K
16x2
0.0
-
0.0
-
ns
TDHTS
32x1
0.0
-
0.0
-
ns
TWSS
WE setup time before clock K
16x2
1.5
-
1.6
-
ns
TWSTS
32x1
1.5
-
1.6
-
ns
TWHS
WE hold time after clock K
16x2
0.0
-
0.0
-
ns
TWHTS
32x1
0.0
-
0.0
-
ns
TWOS
Data valid after clock K
16x2
-
6.5
-
7.9
ns
TWOTS
32x1
-
7.0
-
9.3
ns
Read Operation
TRC
Address read cycle time
16x2
2.6
-
2.6
-
ns
TRCT
32x1
3.8
-
3.8
-
ns
TILO
Data valid after address change (no Write
Enable)
16x2
-
1.2
-
1.6
ns
TIHO
32x1
-
2.0
-
2.7
ns
TICK
Address setup time before clock K
16x2
1.8
-
2.4
-
ns
TIHCK
32x1
2.9
-
3.9
-
ns
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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| XCS20-5CS100C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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相關(guān)代理商/技術(shù)參數(shù) |
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| XCS20-5CS100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-5CS100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-5CS208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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