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| 型號： | XCS20-4PQ144I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 20/82頁 |
| 文件大小： | 863K |
| 代理商： | XCS20-4PQ144I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Master Serial Mode
The Master serial mode uses an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices
and
the
Xilinx
serial-configuration
PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the default
slow frequency, then can switch to the higher frequency dur-
ing the first frame. Frequency tolerance is –50% to +25%.
In Master Serial mode, the CCLK output of the device drives
a Xilinx SPROM that feeds the FPGA DIN input. Each rising
edge of the CCLK output increments the Serial PROM inter-
nal address counter. The next data bit is put on the SPROM
data output, connected to the FPGA DIN pin. The FPGA
accepts this data on the subsequent rising CCLK edge.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in Figure 24.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specifica-
tion section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Devices such as
XC3000A and XC3100A do not support the Fast Configura-
tion Rate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user I/O, but LDC is then
restricted to be a permanently High user output after config-
uration. Using DONE can also avoid contention on DIN, pro-
vided the Early DONE option is invoked.
Figure 25 shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
In this mode, an external signal drives the CCLK input of the
FPGA (most often from a Master Serial device). The serial
configuration bitstream must be available at the DIN input of
the lead FPGA a short setup time before each rising CCLK
edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin. There
is an internal delay of 0.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
FPGA in the daisy chain accepts data on the subsequent
rising CCLK edge.
Figure 25 shows a full master/slave system. A Spartan/XL
device in Slave Serial mode should be connected as shown
in the third device from the left.
Figure 24: Master Serial Mode Programming Switching Characteristics
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
TDSCK
n
n + 1
n + 2
n – 3n – 2n – 1n
TCKDS
DS060_24_080400
Notes:
1.
At power-up, VCC must rise from 2.0V to VCC min in less than 25 ms, otherwise
delay configuration by pulling PROGRAM Low until VCC is valid.
2.
Master Serial mode timing is based on testing in slave mode.
Symbol
Description
Min
Units
CCLK
TDSCK
DIN setup
20
ns
TCKDS
DIN hold
0
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XCS20-4PQ208C | 功能描述:IC FPGA 5V C-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS20-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS20-4PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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