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| 型號： | XCS20-4PQ144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 53/82頁 |
| 文件大小： | 863K |
| 代理商： | XCS20-4PQ144C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and are expressed in nano-
seconds unless otherwise noted.
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Timing
Symbol
Dual Port RAM
Size
-5
-4
Units
Min
Max
Min
Max
Write Operation(1)
TWCDS
Address write cycle time (clock K period)
16x1
7.7
-
8.4
-
ns
TWPDS
Clock K pulse width (active edge)
16x1
3.1
-
3.6
-
ns
TASDS
Address setup time before clock K
16x1
1.3
-
1.5
-
ns
TDSDS
DIN setup time before clock K
16x1
1.7
-
2.0
-
ns
TWSDS
WE setup time before clock K
16x1
1.4
-
1.6
-
ns
All hold times after clock K
16x1
0
-
0
-
ns
TWODS
Data valid after clock K
16x1
-
5.2
-
6.1
ns
Notes:
1.
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Single Port
Dual Port
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSS
TDHS
TASS
TAHS
TWSS
TWPS
TWHS
TWSDS
TWHDS
TWOS
TILO
DS060_34_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSDS
TDHDS
TASDS
TAHDS
TWPDS
TWODS
TILO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS20-4PQ144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ208I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ256C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS20-4PQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ208C | 功能描述:IC FPGA 5V C-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS20-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20-4PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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