參數(shù)資料
型號(hào)： XCS20-4BG256C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 39/82頁(yè)
文件大小： 863K
代理商： XCS20-4BG256C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
44
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
Spartan CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and expressed in nanoseconds
unless otherwise noted.
Symbol
Description
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Clocks
TCH
Clock High time
3.0
-
4.0
-
ns
TCL
Clock Low time
3.0
-
4.0
-
ns
Combinatorial Delays
TILO
F/G inputs to X/Y outputs
-
1.2
-
1.6
ns
TIHO
F/G inputs via H to X/Y outputs
-
2.0
-
2.7
ns
THH1O
C inputs via H1 via H to X/Y outputs
-
1.7
-
2.2
ns
CLB Fast Carry Logic
TOPCY
Operand inputs (F1, F2, G1, G4) to COUT
-1.7
-
2.1
ns
TASCY
Add/Subtract input (F3) to COUT
-2.8
-
3.7
ns
TINCY
Initialization inputs (F1, F3) to COUT
-1.2
-
1.4
ns
TSUM
CIN through function generators to X/Y outputs
-
2.0
-
2.6
ns
TBYP
CIN to COUT, bypass function generators
-
0.5
-
0.6
ns
Sequential Delays
TCKO
Clock K to Flip-Flop outputs Q
-
2.1
-
2.8
ns
Setup Time before Clock K
TICK
F/G inputs
1.8
-
2.4
-
ns
TIHCK
F/G inputs via H
2.9
-
3.9
-
ns
THH1CK
C inputs via H1 through H
2.3
-
3.3
-
ns
TDICK
C inputs via DIN
1.3
-
2.0
-
ns
TECCK
C inputs via EC
2.0
-
2.6
-
ns
TRCK
C inputs via S/R, going Low (inactive)
2.5
-
4.0
-
ns
Hold Time after Clock K
All Hold times, all devices
0.0
-
0.0
-
ns
Set/Reset Direct
TRPW
Width (High)
3.0
-
4.0
-
ns
TRIO
Delay from C inputs via S/R, going High to Q
-
3.0
-
4.0
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
11.5
-
13.5
-
ns
TMRQ
Delay from GSR input to any Q
See page 50 for TRRI values per device.
FTOG
Toggle Frequency (MHz)
(for export control purposes)
-
166
-
125
MHz
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XCS20-4BG256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA
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XCS20-4BG84C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20-4BG84I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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