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    參數(shù)資料
    型號: XCS10XL-4VQG100C
    廠商: Xilinx Inc
    文件頁數(shù): 1/83頁
    文件大?。?/td> 0K
    描述: IC SPARTAN-XL FPGA 10K 100-VQFP
    產(chǎn)品變化通告: Product Discontinuation 26/Oct/2011
    標準包裝: 90
    系列: Spartan®-XL
    LAB/CLB數(shù): 196
    邏輯元件/單元數(shù): 466
    RAM 位總計: 6272
    輸入/輸出數(shù): 77
    門數(shù): 10000
    電源電壓: 3 V ~ 3.6 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 100-TQFP
    供應商設備封裝: 100-VQFP(14x14)
    產(chǎn)品目錄頁面: 599 (CN2011-ZH PDF)
    其它名稱: 122-1291
    DS060 (v2.0) March 1, 2013
    1
    Product Specification
    1998-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
    All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
    Product Obsolete/Under Obsolescence
    Introduction
    The Spartan and the Spartan-XL FPGA families are a
    high-volume production FPGA solution that delivers all the
    key requirements for ASIC replacement up to 40,000 gates.
    These requirements include high performance, on-chip
    RAM, core solutions and prices that, in high volume,
    approach and in many cases are equivalent to mask pro-
    grammed ASIC devices.
    By streamlining the Spartan series feature set, leveraging
    advanced process technologies and focusing on total cost
    management, the Spartan series delivers the key features
    required by ASIC and other high-volume logic users while
    avoiding the initial cost, long development cycles and inher-
    ent risk of conventional ASICs. The Spartan and Spar-
    tan-XL families in the Spartan series have ten members, as
    shown in Table 1.
    Spartan/Spartan-XL FPGA Features
    Note: The Spartan series devices described in this data
    sheet include the 5V Spartan family and the 3.3V
    Spartan-XL family. See the separate data sheets for more
    advanced members for the Spartan Series.
    First ASIC replacement FPGA for high-volume
    production with on-chip RAM
    Density up to 1862 logic cells or 40,000 system gates
    Streamlined feature set based on XC4000 architecture
    System performance beyond 80 MHz
    Broad set of AllianceCORE and LogiCORE
    predefined solutions available
    Unlimited reprogrammability
    Low cost
    System level features
    -
    Available in both 5V and 3.3V versions
    -
    On-chip SelectRAM memory
    -
    Fully PCI compliant
    -
    Full readback capability for program verification
    and internal node observability
    -
    Dedicated high-speed carry logic
    -
    Internal 3-state bus capability
    -
    Eight global low-skew clock or signal networks
    -
    IEEE 1149.1-compatible Boundary Scan logic
    -
    Low cost plastic packages available in all densities
    -
    Footprint compatibility in common packages
    Fully supported by powerful Xilinx ISE Classics
    development system
    -
    Fully automatic mapping, placement and routing
    Additional Spartan-XL Family Features
    3.3V supply for low power with 5V tolerant I/Os
    Power down input
    Higher performance
    Faster carry logic
    More flexible high-speed clock network
    Latch capability in Configurable Logic Blocks
    Input fast capture latch
    Optional MUX or 2-input function generator on outputs
    12 mA or 24 mA output drive
    5V and 3.3V PCI compliant
    Enhanced Boundary Scan
    Express Mode configuration
    0
    Spartan and Spartan-XL FPGA
    Families Data Sheet
    DS060 (v2.0) March 1, 2013
    00
    Product Specification
    R
    Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
    Device
    Logic
    Cells
    Max
    System
    Gates
    Typical
    Gate Range
    (Logic and RAM)(1)
    CLB
    Matrix
    Total
    CLBs
    No. of
    Flip-flops
    Max.
    Avail.
    User I/O
    Total
    Distributed
    RAM Bits
    XCS05 and XCS05XL
    238
    5,000
    2,000-5,000
    10 x 10
    100
    360
    77
    3,200
    XCS10 and XCS10XL
    466
    10,000
    3,000-10,000
    14 x 14
    196
    616
    112
    6,272
    XCS20 and XCS20XL
    950
    20,000
    7,000-20,000
    20 x 20
    400
    1,120
    160
    12,800
    XCS30 and XCS30XL
    1368
    30,000
    10,000-30,000
    24 x 24
    576
    1,536
    192
    18,432
    XCS40 and XCS40XL
    1862
    40,000
    13,000-40,000
    28 x 28
    784
    2,016
    205(2)
    25,088
    Notes:
    1.
    Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
    2.
    XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
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