參數(shù)資料
型號： XCS10XL-4VQ100I
廠商： Xilinx Inc
文件頁數(shù)： 41/83頁
文件大小： 0K
描述： IC FPGA 3.3V I-TEMP 100-VQFP
產(chǎn)品變化通告： Product Discontinuation 26/Oct/2011
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-XL
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計(jì)： 6272
輸入/輸出數(shù)： 77
門數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Spartan and Spartan-XL FPGA Families Data Sheet
46
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
(continued)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Dual Port RAM
Size(1)
-4
-3
Units
Min
Max
Min
Max
Write Operation
TWCDS
Address write cycle time (clock K period)
16x1
8.0
-
11.6
-
ns
TWPDS
Clock K pulse width (active edge)
16x1
4.0
-
5.8
-
ns
TASDS
Address setup time before clock K
16x1
1.5
-
2.1
-
ns
TAHDS
Address hold time after clock K
16x1
0
-
0
-
ns
TDSDS
DIN setup time before clock K
16x1
1.5
-
1.6
-
ns
TDHDS
DIN hold time after clock K
16x1
0
-
0
-
ns
TWSDS
WE setup time before clock K
16x1
1.5
-
1.6
-
ns
TWHDS
WE hold time after clock K
16x1
0
-
0
-
ns
TWODS
Data valid after clock K
16x1
-
6.5
-
7.0
ns
Notes:
1.
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Single Port
Dual Port
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSS
TDHS
TASS
TAHS
TWSS
TWPS
TWHS
TWSDS
TWHDS
TWOS
TILO
DS060_34_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSDS
TDHDS
TASDS
TAHDS
TWPDS
TWODS
TILO
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