- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300147 > XCS10XL-3BG208I (Xilinx, Inc.) Spartan and Spartan-XL Families Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號： | XCS10XL-3BG208I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 29/82頁 |
| 文件大?。?/td> | 863K |
| 代理商： | XCS10XL-3BG208I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
1-800-255-7778
R
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL Express mode, the length count bits are ignored,
and DOUT is held Low, to disable the next device in the
pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL Express mode, when the first device is fully pro-
grammed, DOUT goes High to enable the next device in the
chain.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 30.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL PRO-
GRAM pin has a permanent weak pull-up. Avoid holding
PROGRAM Low for more than 500
s.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
to wait after completing the configuration memory clear
operation. When INIT is no longer held Low externally, the
device determines its configuration mode by capturing the
state of the Mode pins, and is ready to start the configura-
tion process. A master device waits up to an additional
300
s to make sure that any slaves in the optional daisy
chain have seen that INIT is High.
Figure 30: Power-up Configuration Sequence
INIT
High? if
Master
Sample
Mode Line
Load One
Configuration
Data Frame
Frame
Error
Pass
Configuration
Data to DOUT
VCC
Valid
No
Yes
No
Yes
Operational
Start-Up
Sequence
No
Yes
~1.3
s per Frame
Master Delays Before
Sampling Mode Line
Master CCLK
Goes Active
F
Pull INIT Low
and Stop
DS060_30_080400
EXTEST*
SAMPLE/PRELOAD
BYPASS
CONFIGURE*
(* if PROGRAM = High)
SAMPLE/PRELOAD
BYPASS
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
If Boundary Scan
is Selected
Config-
uration
memory
Full
CCLK
Count Equals
Length
Count
Completely Clear
Configuration Memory
Once More
LDC
Output
=
L,
HDC
Output
=
H
Boundary Scan
Instructions
Available:
I/O
Active
Keep Clearing
Configuration
Memory
Test MODE, Generate
One Time-Out Pulse
of 16 or 64 ms
PROGRAM
= Low
No
Yes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS10XL-3BG240C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG256C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG256I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG280I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS10XL-3BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS10XL-3BG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS10XL-3BG280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。