• <pre id="lssnu"><fieldset id="lssnu"></fieldset></pre>
  • <dl id="lssnu"><strike id="lssnu"><wbr id="lssnu"></wbr></strike></dl>
  • <input id="lssnu"><strike id="lssnu"></strike></input>
      參數(shù)資料
      型號: XCS10-3VQ100I
      廠商: Xilinx Inc
      文件頁數(shù): 1/83頁
      文件大?。?/td> 0K
      描述: IC FPGA 5V I-TEMP 100-VQFP
      產(chǎn)品變化通告: Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010
      標(biāo)準(zhǔn)包裝: 90
      系列: Spartan®
      LAB/CLB數(shù): 196
      邏輯元件/單元數(shù): 466
      RAM 位總計(jì): 6272
      輸入/輸出數(shù): 77
      門數(shù): 10000
      電源電壓: 4.5 V ~ 5.5 V
      安裝類型: 表面貼裝
      工作溫度: -40°C ~ 100°C
      封裝/外殼: 100-TQFP
      供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
      DS060 (v2.0) March 1, 2013
      1
      Product Specification
      1998-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
      All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
      Product Obsolete/Under Obsolescence
      Introduction
      The Spartan and the Spartan-XL FPGA families are a
      high-volume production FPGA solution that delivers all the
      key requirements for ASIC replacement up to 40,000 gates.
      These requirements include high performance, on-chip
      RAM, core solutions and prices that, in high volume,
      approach and in many cases are equivalent to mask pro-
      grammed ASIC devices.
      By streamlining the Spartan series feature set, leveraging
      advanced process technologies and focusing on total cost
      management, the Spartan series delivers the key features
      required by ASIC and other high-volume logic users while
      avoiding the initial cost, long development cycles and inher-
      ent risk of conventional ASICs. The Spartan and Spar-
      tan-XL families in the Spartan series have ten members, as
      shown in Table 1.
      Spartan/Spartan-XL FPGA Features
      Note: The Spartan series devices described in this data
      sheet include the 5V Spartan family and the 3.3V
      Spartan-XL family. See the separate data sheets for more
      advanced members for the Spartan Series.
      First ASIC replacement FPGA for high-volume
      production with on-chip RAM
      Density up to 1862 logic cells or 40,000 system gates
      Streamlined feature set based on XC4000 architecture
      System performance beyond 80 MHz
      Broad set of AllianceCORE and LogiCORE
      predefined solutions available
      Unlimited reprogrammability
      Low cost
      System level features
      -
      Available in both 5V and 3.3V versions
      -
      On-chip SelectRAM memory
      -
      Fully PCI compliant
      -
      Full readback capability for program verification
      and internal node observability
      -
      Dedicated high-speed carry logic
      -
      Internal 3-state bus capability
      -
      Eight global low-skew clock or signal networks
      -
      IEEE 1149.1-compatible Boundary Scan logic
      -
      Low cost plastic packages available in all densities
      -
      Footprint compatibility in common packages
      Fully supported by powerful Xilinx ISE Classics
      development system
      -
      Fully automatic mapping, placement and routing
      Additional Spartan-XL Family Features
      3.3V supply for low power with 5V tolerant I/Os
      Power down input
      Higher performance
      Faster carry logic
      More flexible high-speed clock network
      Latch capability in Configurable Logic Blocks
      Input fast capture latch
      Optional MUX or 2-input function generator on outputs
      12 mA or 24 mA output drive
      5V and 3.3V PCI compliant
      Enhanced Boundary Scan
      Express Mode configuration
      0
      Spartan and Spartan-XL FPGA
      Families Data Sheet
      DS060 (v2.0) March 1, 2013
      00
      Product Specification
      R
      Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
      Device
      Logic
      Cells
      Max
      System
      Gates
      Typical
      Gate Range
      (Logic and RAM)(1)
      CLB
      Matrix
      Total
      CLBs
      No. of
      Flip-flops
      Max.
      Avail.
      User I/O
      Total
      Distributed
      RAM Bits
      XCS05 and XCS05XL
      238
      5,000
      2,000-5,000
      10 x 10
      100
      360
      77
      3,200
      XCS10 and XCS10XL
      466
      10,000
      3,000-10,000
      14 x 14
      196
      616
      112
      6,272
      XCS20 and XCS20XL
      950
      20,000
      7,000-20,000
      20 x 20
      400
      1,120
      160
      12,800
      XCS30 and XCS30XL
      1368
      30,000
      10,000-30,000
      24 x 24
      576
      1,536
      192
      18,432
      XCS40 and XCS40XL
      1862
      40,000
      13,000-40,000
      28 x 28
      784
      2,016
      205(2)
      25,088
      Notes:
      1.
      Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
      2.
      XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.
      相關(guān)PDF資料
      PDF描述
      XCS10-3VQ100C IC FPGA 5V C-TEMP 100-VQFP
      XCS10-3TQ144C IC FPGA 5V C-TEMP 144-TQFP
      XCS10-3PC84C IC FPGA 5V C-TEMP 84-PLCC
      XCS05XL-5VQ100C IC FPGA 3.3V C-TEMP 100-VQFP
      XCS05XL-5PC84C IC FPGA 3.3V C-TEMP 84-PLCC
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      XCS10-3VQ144C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
      XCS10-3VQ144I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
      XCS10-3VQ208C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
      XCS10-3VQ208I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
      XCS10-3VQ240C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays