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參數(shù)資料
| 型號： | XCS05XL-5VQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 34/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 100-VQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計： | 3200 |
| 輸入/輸出數(shù)： | 77 |
| 門數(shù)： | 5000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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Spartan and Spartan-XL FPGA Families Data Sheet
4
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
A CLB can implement any of the following functions:
Any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
Note: When three separate functions are generated, one of
the function outputs must be captured in a flip-flop internal to
the CLB. Only two unregistered function generator outputs
are available from the CLB.
Any single function of five variables
Any function of four variables together with some
functions of six variables
Some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
Flip-Flops
Each CLB contains two flip-flops that can be used to regis-
ter (store) the function generator outputs. The flip-flops and
function generators can also be used independently (see
Figure 2). The CLB input DIN can be used as a direct input
to either of the two flip-flops. H1 can also drive either
flip-flop via the H-LUT with a slight additional delay.
The two flip-flops have common clock (CK), clock enable
(EC) and set/reset (SR) inputs. Internally both flip-flops are
also controlled by a global initialization signal (GSR) which
is described in detail in Global Signals: GSR and GTS,
Latches (Spartan-XL Family Only)
The Spartan-XL family CLB storage elements can also be
configured as latches. The two latches have common clock
(K) and clock enable (EC) inputs. Functionality of the stor-
age element is described in Table 2.
Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)
G4
G
H1
F
G4
G3
G2
G1
DYQ
Y
X
SR
CK
EC
Q
G1
SR
H1
DIN
G
H
Logic
Function
of
G1-G4
Logic
Function
of
F-G-H1
Multiplexer Controlled
by Configuration Program
G-LUT
F4
F3
F2
F1
K
EC
G
Logic
Function
of
F1-F4
F-LUT
H-LUT
A
B
DXQ
SR
CK
EC
Q
DS060_02_0506 01
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05XL-5VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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| XCS05XL-5VQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-5VQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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