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參數資料
| 型號： | XCS05XL-4PQ100C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現場可編程門陣列 |
| 文件頁數： | 33/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05XL-4PQ100C |
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R
DS060 (v1.5) March 2, 2000
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4-33
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the Readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the Read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
are listed in
Table 16
and
Table 17
.
Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
computer screen, acting as a low-cost in-circuit emulator.
Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
not measured directly. They are derived from benchmark
timing patterns that are taken at device introduction, prior to
any process improvements.
The following guidelines reflect worst-case values over the
recommended operating conditions.
Note 1:
Note 2:
Timing parameters apply to all speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.
RTRC
T
RCRT
T
RCRT
T
2
2
RCL
T
4
RCRR
T
6
RCH
T
5
RCRD
T
7
DUMMY
DUMMY
rdbk.DATA
rdbk.RIP
rdclk.I
rdbk.TRIG
Finished
Internal Net
VALID
X1790
VALID
1
RTRC
T
1
Spartan and Spartan-XL Readback
Description
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Symbol
T
RTRC
T
RCRT
T
RCRD
T
RCRR
T
RCH
T
RCL
Min
200
50
-
-
250
250
Max
-
-
250
250
500
500
Units
ns
ns
ns
ns
ns
ns
1
2
7
6
5
4
相關PDF資料 |
PDF描述 |
|---|---|
| XCS05-4PQ100I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4VQ100C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4VQ100C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-4VQ100I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4VQ100I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XCS05XL-4PQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PQ144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-4PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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