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| 型號： | XCS05XL-4PC256C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 46/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-4PC256C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
46
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and are expressed in nanosec-
onds unless otherwise noted.
Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
Symbol
Dual Port RAM
Size
(1)
-4
-3
Units
Min
Max
Min
Max
Write Operation
T
WCDS
Address write cycle time (clock K period)
16x1
8.0
-
11.6
-
ns
T
WPDS
Clock K pulse width (active edge)
16x1
4.0
-
5.8
-
ns
T
ASDS
Address setup time before clock K
16x1
1.5
-
2.1
-
ns
T
AHDS
Address hold time after clock K
16x1
0
-
0
-
ns
T
DSDS
DIN setup time before clock K
16x1
1.5
-
1.6
-
ns
T
DHDS
DIN hold time after clock K
16x1
0
-
0
-
ns
T
WSDS
WE setup time before clock K
16x1
1.5
-
1.6
-
ns
T
WHDS
WE hold time after clock K
16x1
0
-
0
-
ns
T
WODS
Data valid after clock K
16x1
-
6.5
-
7.0
ns
Notes:
1.
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Dual Port
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WSDS
T
WHDS
T
WOS
T
ILO
T
ILO
DS060_34_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
T
DSDS
T
DHDS
T
ASDS
T
AHDS
T
WPDS
T
WODS
T
ILO
T
ILO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05XL-4PC256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PC280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PC280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-4PC84C | 功能描述:IC FPGA 3.3V C-TEMP 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-XL 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS05XL-4PC84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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