參數(shù)資料
型號(hào)： XCS05XL-4BG84C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 14/66頁(yè)
文件大?。?/td> 809K
代理商： XCS05XL-4BG84C
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-14
DS060 (v1.5) March 2, 2000
The dual-port RAM signals and the CLB signals from which
they are originally derived are shown in
Table 10
.
The RAM16X1D primitive used to instantiate the dual-port
RAM consists of an upper and a lower 16 x 1 memory array.
The address port labeled A[3:0] supplies both the read and
write addresses for the lower memory array, which behaves
the same as the 16 x 1 single-port RAM array described
previously. Single Port Out (SPO) serves as the data output
for the lower memory. Therefore, SPO reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the upper
memory. The write address for this memory, however,
comes from the address A[3:0]. Dual Port Out (DPO)
serves as the data output for the upper memory. Therefore,
DPO reflects the data at address DPRA[3:0].
By using A[3:0] for the write address and DPRA[3:0] for the
read address, and reading only the DPO output, a FIFO
that can read and write simultaneously is easily generated.
The simultaneous read/write capability possible with the
dual-port RAM can provide twice the effective data through-
put of a single-port RAM alternating read and write opera-
tions.
The timing relationships for the dual-port RAM mode are
shown in
Figure 13
.
Note that write operations to RAM are synchronous
(edge-triggered); however, data access is asynchronous.
Figure 14: Logic Diagram for the Dual-Port RAM
G
G
G
G
16 x 1
RAM
W
S
4
A[3:0]
I
R
S
4
DPRA[3:0]
G
G
G
G
16 x 1
RAM
W
S
R
S
4
4
D
WE
WCLK
G
SPO
WRITE
CONTROL
READ
OUT
DPO
WRITE
CONTROL
READ
OUT
G
G
G
Table 10: Dual-Port RAM Signals
RAM Signal
Function
CLB
Signal
DIN
F
1
-F
4
D
A[3:0]
Data In
Read Address for Single-Port.
Write Address for Single-Port
and Dual-Port.
Read Address for Dual-Port
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by DPRA[3:0])
DPRA[3:0]
WE
WCLK
SPO
G
1
-G
4
SR
K
F
OUT
DPO
G
OUT
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