參數(shù)資料
型號(hào)： XCS05XL-3VQ144I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 45/82頁(yè)
文件大小： 623K
代理商： XCS05XL-3VQ144I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
45
R
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and are expressed in nanosec-
onds unless otherwise noted.
Symbol
Write Operation
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Read Operation
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
Single Port RAM
Size
(1)
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Address write cycle time (clock K period)
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
8.0
8.0
4.0
4.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
1.5
1.5
0.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
11.6
11.6
5.8
5.8
2.0
2.0
0.0
0.0
2.7
1.7
0.0
0.0
1.6
1.6
0.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
6.5
7.0
7.9
9.3
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
1.8
2.9
-
-
2.6
3.8
-
-
2.4
3.9
-
-
ns
ns
ns
ns
ns
ns
Data valid after address change (no Write
Enable)
1.2
2.0
-
-
1.6
2.7
-
-
Address setup time before clock K
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