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參數(shù)資料
| 型號(hào)： | XCS05XL-3VQ100C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | FPGA, 100 CLBS, 2000 GATES, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁數(shù)： | 11/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05XL-3VQ100C |
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R
DS060 (v1.5) March 2, 2000
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4-11
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Single-length lines are connected by way of the program-
mable switch matrices, as shown in
Figure 10
. Routing con-
nectivity is shown in
Figure 8
.
Single-length lines incur a delay whenever they go through
a PSM. Therefore, they are not suitable for routing signals
for long distances. They are normally used to conduct sig-
nals within a localized area and to provide the branching for
nets with fanout greater than one.
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a PSM. Double-length lines are
grouped in pairs with the PSMs staggered, so that each line
goes through a PSM at every other row or column of CLBs
(see
Figure 8
).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances.
Each Spartan/XL device longline has a programmable split-
ter switch at its center. This switch can separate the line
into two independent routing channels, each running half
the width or height of the array.
Routing connectivity of the longlines is shown in
Figure 8
.
The longlines also interface to some 3-state buffers which
is described later in
“
3-State Long Line Drivers
”
on
page 17
.
I/O Routing
Spartan/XL devices have additional routing around the IOB
ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines, and
four longlines.
Global Nets and Buffers
The Spartan/XL devices have dedicated global networks.
These networks are designed to distribute clocks and other
high fanout control signals throughout the devices with min-
imal skew.
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are in
addition to the vertical longlines used for standard intercon-
nect. In the 5V Spartan devices, the four global lines can be
driven by either of two types of global buffers; Primary Glo-
bal buffers (BUFGP) or Secondary Global buffers
(BUFGS). Each of these lines can be accessed by one par-
ticular Primary Global buffer, or by any of the Secondary
Global buffers, as shown in
Figure 11
. In the 3V
Spartan-XL devices, the four global lines can be driven by
any of the eight Global Low-Skew Buffers (BUFGLS). The
clock pins of every CLB and IOB can also be sourced from
local interconnect.
X4
X4
X6604
X4
4
One BUFGP
per Global Line
One BUFGP
per Global Line
Any BUFGS
Any BUFGS
BUFGP
PGCK4
SGCK4
PGCK3
SGCK3
BUFGS
BUFGP
BUFGS
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
BUFGS
BUFGS
BUFGP
BUFGP
SGCK1
PGCK1
SGCK2
PGCK2
IOB
X4
locals
locals
locals
locals
l
l
l
l
l
l
l
l
4
4
4
CLB
CLB
locals
locals
CLB
CLB
locals
locals
Figure 11: 5V Spartan Family Global Net Distribution
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