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| 型號： | XCS05XL-3PQ144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 25/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05XL-3PQ144C |
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R
DS060 (v1.5) March 2, 2000
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4-25
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Express Mode (Spartan-XL only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers (
Figure 27
). A CCLK fre-
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see
Table 16 on
page 28
.) Express mode is selected by a <0X> on the
Mode pins (M1, M0).
The first byte of parallel configuration data must be avail-
able at the D inputs of the FPGA a short setup time before
the second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(
Figure 28
).
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
are in Express mode. A single combined bitstream is used
to configure the chain of Express mode devices. CCLK pins
are tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain.
Frame data is accepted only when CS1 is High and the
device
’
s configuration memory is not already full. The lead
device in the chain has its CS1 input tied High (or floating,
since there is an internal pull-up). The status pin DOUT is
pulled Low after the header is received by all devices, and
remains Low until the device
’
s configuration memory is full.
DOUT is then pulled High to signal the next device in the
chain to accept the configuration data on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
to the DONE pin. User I/Os for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by development system options.)
Since the DONE pin is open-drain and does not drive a
High value, tying the DONE pins of all devices together pre-
vents all devices in the chain from going High until the last
device in the chain has completed its configuration cycle. If
the DONE pin of a device is left unconnected, the device
becomes active as soon as that device has been config-
ured. Because only Spartan-XL, XC4000XLA/XV, and
XC5200 devices support Express mode, only these
devices can be used to form an Express mode daisy chain.
4 T
CCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379
Description
Symbol
Min
20
0
Max
Units
ns
ns
ns
ns
ns
MHz
CCLK
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
1
2
3
4
5
T
DCC
T
CCD
T
CCO
T
CCH
T
CCL
F
CC
30
45
45
10
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
Figure 26: Slave Serial Mode Programming Switching Characteristics
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XCS05XL-3PQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-3PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-3PQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-3PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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