參數(shù)資料
型號(hào)： XCS05XL-3PC208I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 37/66頁(yè)
文件大小： 809K
代理商： XCS05XL-3PC208I
R
DS060 (v1.5) March 2, 2000
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4-37
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and expressed in nanoseconds unless otherwise noted.
Speed Grade
Description
-4
-3
Units
Symbol
Min
Max
Min
Max
Clocks
Clock High time
Clock Low time
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
Sequential Delays
Clock K to Flip-Flop outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H1 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control purposes)
T
CH
T
CL
3.0
3.0
4.0
4.0
ns
ns
T
ILO
T
IHO
T
HH1O
1.2
2.0
1.7
1.6
2.7
2.2
ns
ns
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
1.7
2.8
1.2
2.0
0.5
2.1
3.7
1.4
2.6
0.6
ns
ns
ns
ns
ns
T
CKO
2.1
2.8
ns
T
ICK
T
IHCK
T
HH1CK
T
DICK
T
ECCK
T
RCK
1.8
2.9
2.3
1.3
2.0
2.5
2.4
3.9
3.3
2.0
2.6
4.0
ns
ns
ns
ns
ns
ns
0.0
0.0
ns
T
RPW
T
RIO
3.0
3.0
4.0
4.0
ns
ns
T
MRW
T
MRQ
F
TOG
11.5
See
page 42
for T
RRI
values per device.
166
13.5
ns
125
MHz
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