參數(shù)資料
型號(hào)： XCS05XL-3BG100I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 42/66頁
文件大?。?/td> 809K
代理商： XCS05XL-3BG100I
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-42
DS060 (v1.5) March 2, 2000
Spartan IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Note 1: Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
Note 2: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the
clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Speed Grade
Description
Setup Times - TTL Inputs
(Note 1)
Clock Enable (EC) to Clock (IK), no delay
Pad to Clock (IK), no delay
Hold Times
Clock Enable (EC) to Clock (IK), no delay
All Other Hold Times
Propagation Delays - TTL Inputs
(Note 1)
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Delay Option
T
ECIKD
= T
ECIK
+ T
Delay
T
PICKD
= T
PICK
+ T
Delay
T
PDLI
= T
PLI
+ T
Delay
-4
-3
Units
Symbol
Device
Min
Max
Min
Max
T
ECIK
T
PICK
All devices
All devices
1.6
1.5
2.1
2.0
ns
ns
T
IKEC
All devices
All devices
0.0
0.0
0.9
0.0
ns
ns
T
PID
T
PLI
T
IKRI
T
IKLI
All devices
All devices
All devices
All devices
1.5
2.8
2.7
3.2
2.0
3.6
2.8
3.9
ns
ns
ns
ns
T
Delay
XCS05
XCS10
XCS20
XCS30
XCS40
3.6
3.7
3.8
4.5
5.5
4.0
4.1
4.2
5.0
5.5
ns
ns
ns
ns
ns
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
T
MRW
T
RRI
All devices
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
13.5
ns
ns
ns
ns
ns
ns
9.0
9.5
10.0
10.5
11.0
11.3
11.9
12.5
13.1
13.8
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