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| 型號(hào)： | XCS05-5TQ256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 9/66頁(yè) |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-5TQ256I |
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DS060 (v1.5) March 2, 2000
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4-9
Spartan and Spartan-XL Families Field Programmable Gate Arrays
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Set/Reset
As with the CLB registers, the GSR signal can be used to
set or clear the input and output registers, depending on the
value of the INIT attribute or property. The two flip-flops can
be individually configured to set or clear on reset and after
configuration. Other than the global GSR net, no user-con-
trolled set/reset signal is available to the I/O flip-flops
(
Figure 6
). The choice of set or reset applies to both the ini-
tial state of the flip-flop and the response to the GSR pulse.
Independent Clocks
Separate clock signals are provided for the input (IK) and
output (OK) flip-flops. The clock can be independently
inverted for each flip-flop within the IOB, generating either
falling-edge or rising-edge triggered flip-flops. The clock
inputs for each IOB are independent.
Common Clock Enables
The input and output flip-flops in each IOB have a common
clock enable input (see EC signal in
Figure 6
), which
through configuration, can be activated individually for the
input or output flip-flop, or both. This clock enable operates
exactly like the EC signal on the Spartan/XL CLB. It cannot
be inverted within the IOB.
Routing Channel Description
All internal routing channels are composed of metal seg-
ments with programmable switching points and switching
matrices to implement the desired routing. A structured,
hierarchical matrix of routing channels is provided to
achieve efficient automated routing.
This section describes the routing channels available in
Spartan/XL devices.
Figure 8
shows a general block dia-
gram of the CLB routing channels. The implementation
software automatically assigns the appropriate resources
based on the density and timing requirements of the
design. The following description of the routing channels is
for information only and is simplified with some minor
details omitted. For an exact interconnect description the
designer should open a design in the FPGA Editor and
review the actual connections in this tool.
The routing channels will be discussed as follows;
CLB routing channels which run along each row and
column of the CLB array.
IOB routing channels which form a ring (called a
VersaRing) around the outside of the CLB array. It
connects the I/O with the CLB routing channels.
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Figure 8: Spartan/XL CLB Routing Channels and Interface Block Diagram
CLB
PSM
CLB
PSM
PSM
PSM
PSM
PSM
8 Singles
3 Longs
3 Longs
2 Doubles
2 Doubles
8 Singles
3 Longs
2 Doubles
Rev 1.2
3 Longs
2 Doubles
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| XCS05-5VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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