參數(shù)資料
型號： XCS05-5PC280I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 48/66頁
文件大?。?/td> 809K
代理商： XCS05-5PC280I
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-48
DS060 (v1.5) March 2, 2000
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-5
-4
Units
Size
1
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
7.7
7.7
8.4
8.4
ns
ns
Clock K pulse width (active edge)
16x2
32x1
T
WPS
T
WPTS
3.1
3.1
3.6
3.6
ns
ns
Address setup time before clock K
16x2
32x1
T
ASS
T
ASTS
1.3
1.5
1.5
1.7
ns
ns
DIN setup time before clock K
16x2
32x1
T
DSS
T
DSTS
1.5
1.8
1.7
2.1
ns
ns
WE setup time before clock K
16x2
32x1
T
WSS
T
WSTS
1.4
1.3
1.6
1.5
ns
ns
All hold times after clock K
0.0
0.0
ns
Data valid after clock K
16x2
32x1
T
WOS
T
WOTS
4.5
5.4
5.3
6.3
ns
ns
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
2.6
3.8
3.1
5.5
ns
ns
Data Valid after address change (no Write
Enable)
16x2
32x1
T
ILO
T
IHO
1.0
1.7
1.1
2.0
ns
ns
Address setup time before clock K
16x2
32x1
T
ICK
T
IHCK
0.6
1.3
0.7
1.6
ns
ns
Note 1: Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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