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參數(shù)資料
| 型號： | XCS05-5CS100C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 28/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05-5CS100C |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-28
DS060 (v1.5) March 2, 2000
LEGEND:
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The Spartan-XL
Express mode only supports non-CRC error checking. The
non-CRC
error
checking
end-of-frame field for each frame. For CRC error checking,
the software calculates a running CRC and inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an FPGA includes the last
seven data bits.
tests
for
a
designated
Detection of an error results in the suspension of data load-
ing before DONE goes High, and the pulling down of the
INIT pin. In Master serial mode, CCLK continues to operate
externally. The user must detect INIT and initialize a new
configuration by pulsing the PROGRAM pin Low or cycling
V
CC
.
Cyclic Redundancy Check (CRC) for Configura-
tion and Readback
The Cyclic Redundancy Check is a method of error detec-
tion in data transmission applications. Generally, the trans-
mitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system
performs an identical calculation on the bitstream and com-
pares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in
Table 16
. If a frame data
error is detected during the loading of the FPGA, the con-
figuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
Table 16: Spartan/XL Data Stream Formats
Data Type
Serial Modes
(D0...)
Express Mode
(D0-D7)
(Spartan-XL only)
FFFFh
11110010b
COUNT(23:0)
1
—
11010010b
11111110b
DATA(n-1:0)
11010010b
Fill Byte
Preamble Code
Length Count
Fill Bits
Field Check Code
Start Field
Data Frame
CRC or Constant
Field Check
Extend Write Cycle
—
Postamble
Start-Up Bytes
11111111b
0010b
COUNT(23:0)
1111b
—
0b
DATA(n-1:0)
xxxx (CRC)
or 0110b
FFFFFFFFFFh
—
FFFFFFFFFFFFFFh
2
01111111b
FFh
Unshaded
Light
Dark
Note 1: Not used by configuration logic.
Note 2: Development system may add more start-up
bytes.
Once per bitstream
Once per data frame
Once per device
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相關(guān)PDF資料 |
PDF描述 |
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| XCS05-5CS100I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS144C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS208C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS208I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-5CS100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-5CS208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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