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    參數(shù)資料
    型號(hào): XCS05-4TQ280C
    廠商: Xilinx, Inc.
    英文描述: Spartan and Spartan-XL Families Field Programmable Gate Arrays
    中文描述: 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
    文件頁(yè)數(shù): 45/66頁(yè)
    文件大?。?/td> 809K
    代理商: XCS05-4TQ280C
    R
    DS060 (v1.5) March 2, 2000
    Powered by ICminer.com Electronic-Library Service CopyRight 2003
    4-45
    Spartan and Spartan-XL Families Field Programmable Gate Arrays
    Spartan-XL DC Characteristics Over Operating Conditions
    Note 1:
    Note 2:
    Note 3:
    Note 4:
    Note 5:
    With up to 64 pins simultaneously sinking 12 mA (default mode).
    With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
    With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
    With no output current loads, no active input resistors, and all package pins at V
    CC
    or GND.
    With PWRDWN active.
    Power-on Power Supply Requirements
    Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
    current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the required
    power supply voltage of the device from 0V. The current is highest at the fastest suggested ramp rate (2 ms) and is lowest
    at the slowest allowed ramp rate (50 ms).
    Note 1:
    Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may
    result in larger initialization current.
    This specification applies to Commercial and Industrial grade products only. Advance information based on initial
    characterization.
    Ramp-up Time is measured at 0V to 3.0V. Peak current required lasts less than 3 ms and occurs near the internal power-on
    reset threshold voltage.
    Note 2:
    Note 3:
    Symbol
    Description
    Min
    Typ.
    Max
    Units
    V
    OH
    High-level output voltage @ I
    OH
    =
    4.0 mA, V
    CC
    min (LVTTL)
    High-level output voltage @ I
    OH
    =
    500
    μ
    A, (LVCMOS)
    Low-level output voltage @ I
    OL
    = 12.0 mA, V
    CC
    min (LVTTL)
    (Note 1)
    2.4
    V
    90% V
    CC
    V
    V
    OL
    0.4
    V
    Low-level output voltage @ I
    OL
    = 24.0 mA, V
    CC
    min (LVTTL)
    (Note 2)
    0.4
    V
    Low-level output voltage @ I
    OL
    = 1500
    μ
    A, (LVCMOS)
    Data retention supply voltage (below which configuration data
    may be lost)
    10% V
    CC
    V
    V
    DR
    2.5
    V
    I
    CCO
    I
    CCPD
    I
    L
    C
    IN
    I
    RPU
    I
    RPD
    Quiescent FPGA supply current (Notes 3,4)
    0.1
    5
    mA
    Power Down FPGA supply current (Notes 3,5)
    0.1
    5
    mA
    Input or output leakage current
    10
    +10
    μ
    A
    Input capacitance (sample tested)
    10
    pF
    Pad pull-up (when selected) @ V
    IN
    = 0V (sample tested)
    Pad pull-down (when selected) @ V
    IN
    = 3.3V (sample tested)
    0.02
    0.25
    mA
    0.02
    mA
    Product
    Description
    Ramp-up Time
    Fast (2 ms)
    100 mA
    Slow (50 ms)
    100 mA
    Spartan-XL Family
    Minimum required current supply
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