參數(shù)資料
      型號(hào)： XCS05-4TQ240C
      廠商： Xilinx, Inc.
      英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
      中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
      文件頁(yè)數(shù)： 29/66頁(yè)
      文件大小： 809K
      代理商： XCS05-4TQ240C
      R
      DS060 (v1.5) March 2, 2000
      Powered by ICminer.com Electronic-Library Service CopyRight 2003
      4-29
      Spartan and Spartan-XL Families Field Programmable Gate Arrays
      During Readback, 11 bits of the 16-bit checksum are added
      to the end of the Readback data stream. The checksum is
      computed using the CRC-16 CCITT polynomial, as shown
      in
      Figure 29
      . The checksum consists of the 11 most signifi-
      cant bits of the 16-bit code. A change in the checksum indi-
      cates a change in the Readback bitstream. A comparison
      to a previous checksum is meaningful only if the readback
      data is independent of the current device state. CLB out-
      puts should not be included (Readback Capture option not
      used), and if RAM is present, the RAM content must be
      unchanged.
      Statistically, one error out of 2048 might go undetected.
      Configuration Sequence
      There are four major steps in the Spartan/XL power-up
      configuration sequence.
      Configuration Memory Clear
      Initialization
      Configuration
      Start-up
      The full process is illustrated in
      Figure 30
      .
      Configuration Memory Clear
      When power is first applied or is reapplied to an FPGA, an
      internal circuit forces initialization of the configuration logic.
      When V
      CC
      reaches an operational level, and the circuit
      passes the write and read test of a sample pair of configu-
      ration bits, a time delay is started. This time delay is nomi-
      nally 16 ms. The delay is four times as long when in Master
      Serial Mode to allow ample time for all slaves to reach a
      stable V
      CC
      . When all INIT pins are tied together, as recom-
      mended, the longest delay takes precedence. Therefore,
      devices with different time delays can easily be mixed and
      matched in a daisy chain.
      This delay is applied only on power-up. It is not applied
      when reconfiguring an FPGA by pulsing the PROGRAM pin
      Table 17: Spartan/XL Program Data
      Device
      XCS05
      5,000
      XCS10
      10,000
      XCS20
      20,000
      XCS30
      30,000
      XCS40
      40,000
      Max System
      Gates
      CLBs
      (Row x Col.)
      IOBs
      Part Number
      Supply Voltage
      Bits per Frame
      Frames
      Program Data
      PROM Size
      (bits)
      Serial PROM
      Express Mode
      PROM Size
      (bits)
      Notes: 1.Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits (+ 1 for
      Spartan-XL device)
      Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 (+ 1 for Spartan-XL device)
      Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
      PROM Size = Program Data + 40 (header) + 8, rounded up to the nearest byte
      2.The user can add more "1" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any
      frame, following the four error check bits. However, the Length Count value
      must
      be adjusted for all such extra "one" bits,
      even for extra leading ones at the beginning of the header.
      3. Express mode adds 57 (XCS05XL, XCS10XL), or 53 (XCS20XL, XCS30XL, XCS40XL) bits per frame, + 24 additional bits.
      100
      (10 x 10)
      80
      XCS05
      5V
      126
      428
      53,936
      53,984
      196
      (14 x 14)
      112
      XCS10
      5V
      166
      572
      94,960
      95,008
      400
      (20 x 20)
      160
      XCS20
      5V
      226
      788
      178,096
      178,144
      576
      (24 x 24)
      192
      XCS30
      5V
      266
      932
      247,920
      247,968
      784
      (28 x 28)
      224
      XCS40
      5V
      306
      1,076
      329,264
      329,312
      XCS05XL
      3.3V
      127
      429
      54,491
      54,536
      XCS10XL
      3.3V
      167
      573
      95,699
      95,744
      XCS20XL
      3.3V
      227
      789
      179,111
      179,160
      XCS30XL
      3.3V
      267
      933
      249,119
      249,168
      XCS40XL
      3.3V
      307
      1,077
      330,647
      330,696
      17S05
      17S05XL
      79,064
      17S10
      17S10XL
      128,480
      17S20
      17S20XL
      221,048
      17S30
      17S30XL
      298,688
      17S40
      17S40XL
      387,848
      Figure 29: Circuit for Generating CRC-16
      0
      X2
      2
      3
      4
      5
      6
      7
      8
      9 10 11 12 13 14
      1
      X15
      X16
      15
      SERIAL DATA IN
      1
      0 15 14 13 12 11 10 9
      8
      7
      6
      5
      1
      1
      1
      1
      CRC
      –
      CHECKSUM
      LAST DATA FRAME
      S
      X1789
      Polynomial: X16 + X15 + X2 + 1
      Readback Data Stream
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