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參數(shù)資料
| 型號： | XCS05-3VQ280I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 7/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3VQ280I |
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R
DS060 (v1.5) March 2, 2000
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4-7
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL V
CC
Clamping
Spartan-XL FPGAs have an optional clamping diode con-
nected from each I/O to V
CC
. When enabled they clamp
ringing transients back to the 3.3V supply rail. This clamp-
ing action is required in 3.3V PCI applications. V
CC
clamp-
ing is a global option affecting all I/O pins.
Spartan-XL devices are fully 5V TTL I/O compatible if V
CC
clamping is not enabled. With V
CC
clamping enabled, the
Spartan-XL devices will begin to clamp input voltages to
one diode voltage drop above V
CC
. If enabled, TTL I/O
compatibility is maintained but full 5V I/O tolerance is sacri-
ficed. The user may select either 5V tolerance (default) or
3.3V PCI compatibility. In both cases negative voltage is
clamped to one diode voltage drop below ground.
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in
Table 5
.
Additional Fast Capture Input Latch (Spartan-XL only)
The Spartan-XL IOB has an additional optional latch on the
input. This latch is clocked by the clock used for the output
flip-flop rather than the input clock. Therefore, two different
clocks can be used to clock the two input storage elements.
This additional latch allows the fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele-
ment, and the inverter is absorbed into the IOB.
IOB Output Signal Path
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in
Table 6
.
Output Multiplexer/2-Input Function Generator
(Spartan-XL only)
The output path in the Spartan-XL IOB contains an addi-
tional multiplexer not available in the Spartan IOB. The mul-
tiplexer can also be configured as a 2-input function
generator, implementing a pass gate, AND gate, OR gate,
or XOR gate, with 0, 1, or 2 inverted inputs.
Table 4: Supported Sources for Spartan/XL Inputs
Source
Spartan
Inputs
5V,
TTL
Spartan-XL
Inputs
3.3V
CMOS
5V,
CMOS
Any device, V
CC
= 3.3V,
CMOS outputs
Spartan family, V
CC
= 5V,
TTL outputs
Any device, V
CC
= 5V,
TTL outputs (V
OH
≤
3.7V)
Any device, V
CC
= 5V,
CMOS outputs
√
Unreli-
able
Data
√
√
√
√
√
√
√
√
(default
mode)
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
TTL
LVTTL
PCI5V
PCI3V
LVCMOS 3V
VCC
Clamping
Not allowed
OK
Not allowed
Required
OK
Output Drive
12/24 mA
12/24 mA
24 mA
12 mA
12/24 mA
V
IH MAX
5.5
3.6
5.5
3.6
3.6
V
IH MIN
2.0
2.0
2.0
50% of V
CC
50% of V
CC
V
IL MAX
0.8
0.8
0.8
30% of V
CC
30% of V
CC
V
OH MIN
2.4
2.4
2.4
90% of V
CC
90% of V
CC
V
OL MAX
0.4
0.4
0.4
10% of V
CC
10% of V
CC
Table 6: Output Flip-Flop Functionality
Mode
Power-Up
or GSR
Clock
X
Clock
Enable
X
T
0*
D
X
Q
SR
Flip-Flop
X
0
1*
X
X
0*
0*
1
0*
X
D
X
X
Q
D
Z
Q
__/
X
0
Legend:
X
__/
SR
0*
1*
Z
Don
’
t care
Rising edge (clock not inverted)
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
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